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authorRex Zhu <Rex.Zhu@amd.com>2017-01-10 15:00:40 +0300
committerAlex Deucher <alexander.deucher@amd.com>2017-01-17 23:24:55 +0300
commite05208ded1905e500cd5b369d624b071951c68b9 (patch)
tree6bd806bd2b10604cf6454c5f4ba468bd2ed0aa5a /drivers/gpu
parent69bcc0b7140c30de552aa3ef08322295862e8e2f (diff)
downloadlinux-e05208ded1905e500cd5b369d624b071951c68b9.tar.xz
drm/amdgpu: fix bug set incorrect value to vce register
Set the proper bits for clockgating setup. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vce_v3_0.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
index 5fb0b7f5c065..b621bde8c240 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
@@ -175,7 +175,7 @@ static void vce_v3_0_set_vce_sw_clock_gating(struct amdgpu_device *adev,
WREG32(mmVCE_UENC_CLOCK_GATING_2, data);
data = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
- data &= ~0xffc00000;
+ data &= ~0x3ff;
WREG32(mmVCE_UENC_REG_CLOCK_GATING, data);
data = RREG32(mmVCE_UENC_DMA_DCLK_CTRL);