diff options
| author | Jonathan Marek <jonathan@marek.ca> | 2021-02-08 21:55:54 +0300 |
|---|---|---|
| committer | Rob Clark <robdclark@chromium.org> | 2021-02-23 23:41:46 +0300 |
| commit | 65aee407a0f5d0548c560e5fc3cad21e51b6f7fd (patch) | |
| tree | fa5b8b66250ee8e6fa0a12650e615eb88f458459 /drivers/gpu | |
| parent | 743c97ca9dc989b0b08ca1fbfd134a83b37fe9ec (diff) | |
| download | linux-65aee407a0f5d0548c560e5fc3cad21e51b6f7fd.tar.xz | |
drm/msm: fix a6xx_gmu_clear_oob
The cleanup patch broke a6xx_gmu_clear_oob, fix it by adding the missing
bitshift operation.
Fixes: 555c50a4a19b ("drm/msm: Clean up GMU OOB set/clear handling")
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index 9066e98eb8ef..863047b98bf3 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -339,7 +339,7 @@ void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state) else bit = a6xx_gmu_oob_bits[state].ack_new; - gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, bit); + gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 1 << bit); } /* Enable CPU control of SPTP power power collapse */ |