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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2022-05-03 21:22:39 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2022-05-31 21:04:46 +0300 |
| commit | 4f543d664cec7e9b490bca55f57151afe6f5cf47 (patch) | |
| tree | 5e23dce6eca72359c54db95a397eb0d736bb74c8 /drivers/gpu | |
| parent | f2206df8ec862073995f5d27f0f55f698843a9b8 (diff) | |
| download | linux-4f543d664cec7e9b490bca55f57151afe6f5cf47.tar.xz | |
drm/i915: Require an exact DP link freq match for the DG2 PLL
No idea why the DG2 PLL DP link frequency calculation is allowing
a non-exact match. That makes no sense so get rid of it.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220503182242.18797-24-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Acked-by: Matt Roper <matthew.d.roper@intel.com>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_snps_phy.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c index cc1270978b67..b48f42f1832a 100644 --- a/drivers/gpu/drm/i915/display/intel_snps_phy.c +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c @@ -629,7 +629,7 @@ int intel_mpllb_calc_state(struct intel_crtc_state *crtc_state, return -EINVAL; for (i = 0; tables[i]; i++) { - if (crtc_state->port_clock <= tables[i]->clock) { + if (crtc_state->port_clock == tables[i]->clock) { crtc_state->mpllb_state = *tables[i]; return 0; } |