diff options
| author | José Roberto de Souza <jose.souza@intel.com> | 2019-08-21 01:33:25 +0300 |
|---|---|---|
| committer | José Roberto de Souza <jose.souza@intel.com> | 2019-08-22 23:09:24 +0300 |
| commit | df7415bfc06f8ee482a510aea39c12121e409dcc (patch) | |
| tree | 7d7961909c580cd81ef0df13cedce71b14704bf5 /drivers/gpu/drm | |
| parent | 99fc38b12095cd0ca9fc5b8c8e27e827dff6ed34 (diff) | |
| download | linux-df7415bfc06f8ee482a510aea39c12121e409dcc.tar.xz | |
drm/i915: Do not unmask PSR interruption in IRQ postinstall
No need to unmask PSR interrutpion if PSR is not enabled, better move
the call to intel_psr_enable_source().
v2: Renamed intel_psr_irq_control() to psr_irq_control() (Lucas)
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190820223325.27490-3-jose.souza@intel.com
Diffstat (limited to 'drivers/gpu/drm')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_psr.c | 6 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_psr.h | 1 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/i915_irq.c | 2 |
3 files changed, 4 insertions, 5 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 771d9a40bf12..28b62e587204 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -105,7 +105,7 @@ static int edp_psr_shift(enum transcoder cpu_transcoder) } } -void intel_psr_irq_control(struct drm_i915_private *dev_priv, u32 debug) +static void psr_irq_control(struct drm_i915_private *dev_priv, u32 debug) { u32 debug_mask, mask; enum transcoder cpu_transcoder; @@ -736,6 +736,8 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp, mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE; I915_WRITE(EDP_PSR_DEBUG(dev_priv->psr.transcoder), mask); + + psr_irq_control(dev_priv, dev_priv->psr.debug); } static void intel_psr_enable_locked(struct drm_i915_private *dev_priv, @@ -1108,7 +1110,7 @@ int intel_psr_debug_set(struct drm_i915_private *dev_priv, u64 val) old_mode = dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK; dev_priv->psr.debug = val; - intel_psr_irq_control(dev_priv, dev_priv->psr.debug); + psr_irq_control(dev_priv, dev_priv->psr.debug); mutex_unlock(&dev_priv->psr.lock); diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h index dc818826f36d..46e4de8b8cd5 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.h +++ b/drivers/gpu/drm/i915/display/intel_psr.h @@ -30,7 +30,6 @@ void intel_psr_flush(struct drm_i915_private *dev_priv, void intel_psr_init(struct drm_i915_private *dev_priv); void intel_psr_compute_config(struct intel_dp *intel_dp, struct intel_crtc_state *crtc_state); -void intel_psr_irq_control(struct drm_i915_private *dev_priv, u32 debug); void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir); void intel_psr_short_pulse(struct intel_dp *intel_dp); int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state, diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 37e3dd3c1a9d..77391d8325bf 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -3684,7 +3684,6 @@ static void ironlake_irq_postinstall(struct drm_i915_private *dev_priv) if (IS_HASWELL(dev_priv)) { gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR); - intel_psr_irq_control(dev_priv, dev_priv->psr.debug); display_mask |= DE_EDP_PSR_INT_HSW; } @@ -3795,7 +3794,6 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) de_port_enables |= GEN8_PORT_DP_A_HOTPLUG; gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR); - intel_psr_irq_control(dev_priv, dev_priv->psr.debug); for_each_pipe(dev_priv, pipe) { dev_priv->de_irq_mask[pipe] = ~de_pipe_masked; |