diff options
| author | Lucas De Marchi <lucas.demarchi@intel.com> | 2023-04-28 01:32:48 +0300 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2023-12-20 02:32:15 +0300 |
| commit | d9b79ad275e7a98c566b3ac4b32950142d6bf9ad (patch) | |
| tree | 787a2885b7b78c60c71bb33345d61f09a7c3926b /drivers/gpu/drm/xe/xe_gt_mcr.c | |
| parent | 7b829f6dd638c2cb45c7710bc7cd1d0395ea9bc1 (diff) | |
| download | linux-d9b79ad275e7a98c566b3ac4b32950142d6bf9ad.tar.xz | |
drm/xe: Drop gen afixes from registers
The defines for the registers were brought over from i915 while
bootstrapping the driver. As xe supports TGL and later only, it doesn't
make sense to keep the GEN* prefixes and suffixes in the registers: TGL
is graphics version 12, previously called "GEN12". So drop the prefix
everywhere.
v2:
- Also drop _TGL suffix and reword commit message as suggested
by Matt Roper. While at it, rename VSUNIT_CLKGATE_DIS_TGL to
VSUNIT_CLKGATE2_DIS with the additional "2", so it doesn't clash
with the define for the other register
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20230427223256.1432787-3-lucas.demarchi@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/xe/xe_gt_mcr.c')
| -rw-r--r-- | drivers/gpu/drm/xe/xe_gt_mcr.c | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.c b/drivers/gpu/drm/xe/xe_gt_mcr.c index 5412f77bc26f..aa04ba5a6dbe 100644 --- a/drivers/gpu/drm/xe/xe_gt_mcr.c +++ b/drivers/gpu/drm/xe/xe_gt_mcr.c @@ -177,8 +177,8 @@ static const struct xe_mmio_range dg2_implicit_steering_table[] = { static void init_steering_l3bank(struct xe_gt *gt) { if (GRAPHICS_VERx100(gt_to_xe(gt)) >= 1270) { - u32 mslice_mask = REG_FIELD_GET(GEN12_MEML3_EN_MASK, - xe_mmio_read32(gt, GEN10_MIRROR_FUSE3.reg)); + u32 mslice_mask = REG_FIELD_GET(MEML3_EN_MASK, + xe_mmio_read32(gt, MIRROR_FUSE3.reg)); u32 bank_mask = REG_FIELD_GET(GT_L3_EXC_MASK, xe_mmio_read32(gt, XEHP_FUSE4.reg)); @@ -190,8 +190,8 @@ static void init_steering_l3bank(struct xe_gt *gt) gt->steering[L3BANK].instance_target = bank_mask & BIT(0) ? 0 : 2; } else if (gt_to_xe(gt)->info.platform == XE_DG2) { - u32 mslice_mask = REG_FIELD_GET(GEN12_MEML3_EN_MASK, - xe_mmio_read32(gt, GEN10_MIRROR_FUSE3.reg)); + u32 mslice_mask = REG_FIELD_GET(MEML3_EN_MASK, + xe_mmio_read32(gt, MIRROR_FUSE3.reg)); u32 bank = __ffs(mslice_mask) * 8; /* @@ -202,8 +202,8 @@ static void init_steering_l3bank(struct xe_gt *gt) gt->steering[L3BANK].group_target = (bank >> 2) & 0x7; gt->steering[L3BANK].instance_target = bank & 0x3; } else { - u32 fuse = REG_FIELD_GET(GEN10_L3BANK_MASK, - ~xe_mmio_read32(gt, GEN10_MIRROR_FUSE3.reg)); + u32 fuse = REG_FIELD_GET(L3BANK_MASK, + ~xe_mmio_read32(gt, MIRROR_FUSE3.reg)); gt->steering[L3BANK].group_target = 0; /* unused */ gt->steering[L3BANK].instance_target = __ffs(fuse); @@ -212,8 +212,8 @@ static void init_steering_l3bank(struct xe_gt *gt) static void init_steering_mslice(struct xe_gt *gt) { - u32 mask = REG_FIELD_GET(GEN12_MEML3_EN_MASK, - xe_mmio_read32(gt, GEN10_MIRROR_FUSE3.reg)); + u32 mask = REG_FIELD_GET(MEML3_EN_MASK, + xe_mmio_read32(gt, MIRROR_FUSE3.reg)); /* * mslice registers are valid (not terminated) if either the meml3 @@ -329,8 +329,8 @@ void xe_gt_mcr_set_implicit_defaults(struct xe_gt *gt) struct xe_device *xe = gt_to_xe(gt); if (xe->info.platform == XE_DG2) { - u32 steer_val = REG_FIELD_PREP(GEN11_MCR_SLICE_MASK, 0) | - REG_FIELD_PREP(GEN11_MCR_SUBSLICE_MASK, 2); + u32 steer_val = REG_FIELD_PREP(MCR_SLICE_MASK, 0) | + REG_FIELD_PREP(MCR_SUBSLICE_MASK, 2); xe_mmio_write32(gt, MCFG_MCR_SELECTOR.reg, steer_val); xe_mmio_write32(gt, SF_MCR_SELECTOR.reg, steer_val); @@ -448,9 +448,9 @@ static u32 rw_with_mcr_steering(struct xe_gt *gt, i915_mcr_reg_t reg, u8 rw_flag steer_val = REG_FIELD_PREP(MTL_MCR_GROUPID, group) | REG_FIELD_PREP(MTL_MCR_INSTANCEID, instance); } else { - steer_reg = GEN8_MCR_SELECTOR.reg; - steer_val = REG_FIELD_PREP(GEN11_MCR_SLICE_MASK, group) | - REG_FIELD_PREP(GEN11_MCR_SUBSLICE_MASK, instance); + steer_reg = MCR_SELECTOR.reg; + steer_val = REG_FIELD_PREP(MCR_SLICE_MASK, group) | + REG_FIELD_PREP(MCR_SUBSLICE_MASK, instance); } /* @@ -461,7 +461,7 @@ static u32 rw_with_mcr_steering(struct xe_gt *gt, i915_mcr_reg_t reg, u8 rw_flag * No need to save old steering reg value. */ if (rw_flag == MCR_OP_READ) - steer_val |= GEN11_MCR_MULTICAST; + steer_val |= MCR_MULTICAST; xe_mmio_write32(gt, steer_reg, steer_val); @@ -477,7 +477,7 @@ static u32 rw_with_mcr_steering(struct xe_gt *gt, i915_mcr_reg_t reg, u8 rw_flag * operation. */ if (rw_flag == MCR_OP_WRITE) - xe_mmio_write32(gt, steer_reg, GEN11_MCR_MULTICAST); + xe_mmio_write32(gt, steer_reg, MCR_MULTICAST); return val; } |