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| author | Riana Tauro <riana.tauro@intel.com> | 2024-05-24 10:09:16 +0300 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2024-05-28 19:29:43 +0300 |
| commit | 38e8c4184ea0eebe478a9e6fc8d1062561223429 (patch) | |
| tree | bad0e89727b1f236c61acd934a63a0dd35fe92fe /drivers/gpu/drm/xe/xe_gt_idle.h | |
| parent | 9276bcc22f52ab52ae77b7b19133943d88b9a3f8 (diff) | |
| download | linux-38e8c4184ea0eebe478a9e6fc8d1062561223429.tar.xz | |
drm/xe: Enable Coarse Power Gating
Enable power gating for all units and sub-pipes that
are disabled by default.
v2: change the init function name
use symmetric calls for enable/disable pg
re-pharase commit message (Rodrigo)
modify the sub-pipe power gating condition
v3: set hysteresis value for render and media
when GuC PC is disabled
skip CPG for PVC (Vinay)
v4: rebase
Signed-off-by: Riana Tauro <riana.tauro@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> #v2
Reviewed-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240524070916.143022-3-riana.tauro@intel.com
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/xe/xe_gt_idle.h')
| -rw-r--r-- | drivers/gpu/drm/xe/xe_gt_idle.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/gpu/drm/xe/xe_gt_idle.h b/drivers/gpu/drm/xe/xe_gt_idle.h index 75bd99659b1b..554447b5d46d 100644 --- a/drivers/gpu/drm/xe/xe_gt_idle.h +++ b/drivers/gpu/drm/xe/xe_gt_idle.h @@ -10,8 +10,10 @@ struct xe_gt; -int xe_gt_idle_sysfs_init(struct xe_gt_idle *gtidle); +int xe_gt_idle_init(struct xe_gt_idle *gtidle); void xe_gt_idle_enable_c6(struct xe_gt *gt); void xe_gt_idle_disable_c6(struct xe_gt *gt); +void xe_gt_idle_enable_pg(struct xe_gt *gt); +void xe_gt_idle_disable_pg(struct xe_gt *gt); #endif /* _XE_GT_IDLE_H_ */ |