diff options
| author | Thierry Reding <treding@nvidia.com> | 2015-09-08 17:09:22 +0300 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2016-07-04 12:33:21 +0300 |
| commit | c31efa7a30ed04cbd17cac6e8fc91fce425773cd (patch) | |
| tree | 74b2215c84be94b01007aa465c84b937a228dd06 /drivers/gpu/drm/tegra/sor.h | |
| parent | 2bd1dd399fcd2e23efb1583df3ba846b20429739 (diff) | |
| download | linux-c31efa7a30ed04cbd17cac6e8fc91fce425773cd.tar.xz | |
drm/tegra: sor: Do not support deep color modes
Current generations of Tegra do not support deep color modes, so force
8 bits per color even if the connected monitor or panel supports more.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/gpu/drm/tegra/sor.h')
| -rw-r--r-- | drivers/gpu/drm/tegra/sor.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/tegra/sor.h b/drivers/gpu/drm/tegra/sor.h index 2d31d027e3f6..865c73b48968 100644 --- a/drivers/gpu/drm/tegra/sor.h +++ b/drivers/gpu/drm/tegra/sor.h @@ -27,6 +27,9 @@ #define SOR_STATE_ASY_PIXELDEPTH_MASK (0xf << 17) #define SOR_STATE_ASY_PIXELDEPTH_BPP_18_444 (0x2 << 17) #define SOR_STATE_ASY_PIXELDEPTH_BPP_24_444 (0x5 << 17) +#define SOR_STATE_ASY_PIXELDEPTH_BPP_30_444 (0x6 << 17) +#define SOR_STATE_ASY_PIXELDEPTH_BPP_36_444 (0x8 << 17) +#define SOR_STATE_ASY_PIXELDEPTH_BPP_48_444 (0x9 << 17) #define SOR_STATE_ASY_VSYNCPOL (1 << 13) #define SOR_STATE_ASY_HSYNCPOL (1 << 12) #define SOR_STATE_ASY_PROTOCOL_MASK (0xf << 8) |