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authorSascha Hauer <s.hauer@pengutronix.de>2023-02-16 13:24:47 +0300
committerHeiko Stuebner <heiko@sntech.de>2023-03-09 03:14:27 +0300
commitd13b10ec6696b0c523fa21b65c7ff6f246a49560 (patch)
treebd0c4cda3a9cdc5dbc77f2a213abdcb8c9bee4d0 /drivers/gpu/drm/rockchip
parent83b61f817f43ed67572d1e241c9f552e0a8bfff4 (diff)
downloadlinux-d13b10ec6696b0c523fa21b65c7ff6f246a49560.tar.xz
drm/rockchip: dw_hdmi: discard modes with unachievable pixelclocks
The Rockchip PLL drivers are currently table based and support only the most common pixelclocks. Discard all modes we cannot achieve at all. Normally the desired pixelclocks have an exact match in the PLL driver, nevertheless allow for a 0.1% error just in case. Tested-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com> Tested-by: Michael Riesch <michael.riesch@wolfvision.net> Tested-by: Dan Johansen <strit@manjaro.org> Link: https://lore.kernel.org/r/20230118132213.2911418-4-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://patchwork.freedesktop.org/patch/msgid/20230216102447.582905-5-s.hauer@pengutronix.de
Diffstat (limited to 'drivers/gpu/drm/rockchip')
-rw-r--r--drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
index feba6b9becd6..293dcf0f0593 100644
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
@@ -260,6 +260,13 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *dw_hdmi, void *data,
bool exact_match = hdmi->plat_data->phy_force_vendor;
int i;
+ if (hdmi->ref_clk) {
+ int rpclk = clk_round_rate(hdmi->ref_clk, pclk);
+
+ if (abs(rpclk - pclk) > pclk / 1000)
+ return MODE_NOCLOCK;
+ }
+
for (i = 0; mpll_cfg[i].mpixelclock != (~0UL); i++) {
/*
* For vendor specific phys force an exact match of the pixelclock