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| author | Alex Deucher <alexander.deucher@amd.com> | 2015-12-17 18:23:34 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2015-12-22 00:39:02 +0300 |
| commit | 092c96a8ab9d1bd60ada2ed385cc364ce084180e (patch) | |
| tree | 5d54ecac3886f9f3eee6444b71b22220c75a601a /drivers/gpu/drm/radeon/radeon_mode.h | |
| parent | 41869c1c7fe583dec932eb3d87de2e010b30a737 (diff) | |
| download | linux-092c96a8ab9d1bd60ada2ed385cc364ce084180e.tar.xz | |
drm/radeon: fix dp link rate selection (v2)
Need to properly handle the max link rate in the dpcd.
This prevents some cases where 5.4 Ghz is selected when
it shouldn't be.
v2: simplify logic, add array bounds check
Reviewed-by: Tom St Denis <tom.stdenis@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_mode.h')
| -rw-r--r-- | drivers/gpu/drm/radeon/radeon_mode.h | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h index d8babb802063..2c8331078529 100644 --- a/drivers/gpu/drm/radeon/radeon_mode.h +++ b/drivers/gpu/drm/radeon/radeon_mode.h @@ -756,8 +756,10 @@ extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector); extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector); extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder, struct drm_connector *connector); -int radeon_dp_get_max_link_rate(struct drm_connector *connector, - const u8 *dpcd); +extern int radeon_dp_get_dp_link_config(struct drm_connector *connector, + const u8 *dpcd, + unsigned pix_clock, + unsigned *dp_lanes, unsigned *dp_rate); extern void radeon_dp_set_rx_power_state(struct drm_connector *connector, u8 power_state); extern void radeon_dp_aux_init(struct radeon_connector *radeon_connector); |