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authorMaxime Ripard <maxime@cerno.tech>2021-09-14 10:25:30 +0300
committerMaxime Ripard <maxime@cerno.tech>2021-09-14 10:25:30 +0300
commit2f76520561d01a5f37e6d6ed2c2e441b6a355a96 (patch)
tree692f210145f35ec2621e2015d788267f25e673cb /drivers/gpu/drm/radeon/radeon_fence.c
parent617d5b34f22c66fe9fc9f150be27f5de1b87ca15 (diff)
parent6880fa6c56601bb8ed59df6c30fd390cc5f6dd8f (diff)
downloadlinux-2f76520561d01a5f37e6d6ed2c2e441b6a355a96.tar.xz
Merge drm/drm-next into drm-misc-next
Kickstart new drm-misc-next cycle. Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_fence.c')
-rw-r--r--drivers/gpu/drm/radeon/radeon_fence.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_fence.c b/drivers/gpu/drm/radeon/radeon_fence.c
index 3f351d222cbb..73e3117420bf 100644
--- a/drivers/gpu/drm/radeon/radeon_fence.c
+++ b/drivers/gpu/drm/radeon/radeon_fence.c
@@ -50,7 +50,7 @@
* for GPU/CPU synchronization. When the fence is written,
* it is expected that all buffers associated with that fence
* are no longer in use by the associated ring on the GPU and
- * that the the relevant GPU caches have been flushed. Whether
+ * that the relevant GPU caches have been flushed. Whether
* we use a scratch register or memory location depends on the asic
* and whether writeback is enabled.
*/