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| author | Alex Deucher <alexander.deucher@amd.com> | 2013-01-25 00:00:17 +0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2013-02-01 01:24:58 +0400 |
| commit | 24178ec42b0985d485886bc43b97e54ff173627e (patch) | |
| tree | 7179ec2f9c917fb36477feb4a12e0d9b53c6e22d /drivers/gpu/drm/radeon/evergreen.c | |
| parent | 123bc1832c33218dfa677a88c2c54bc1a48a9e72 (diff) | |
| download | linux-24178ec42b0985d485886bc43b97e54ff173627e.tar.xz | |
drm/radeon: don't reset the MC on IGPs/APUs
The MC isn't part of the GPU per se.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/evergreen.c')
| -rw-r--r-- | drivers/gpu/drm/radeon/evergreen.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index 045955d5f337..2916de896a60 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c @@ -2500,8 +2500,10 @@ static void evergreen_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) if (reset_mask & RADEON_RESET_VMC) srbm_soft_reset |= SOFT_RESET_VMC; - if (reset_mask & RADEON_RESET_MC) - srbm_soft_reset |= SOFT_RESET_MC; + if (!(rdev->flags & RADEON_IS_IGP)) { + if (reset_mask & RADEON_RESET_MC) + srbm_soft_reset |= SOFT_RESET_MC; + } if (grbm_soft_reset) { tmp = RREG32(GRBM_SOFT_RESET); |