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authorAlexandre Courbot <acourbot@nvidia.com>2017-02-23 12:41:41 +0300
committerBen Skeggs <bskeggs@redhat.com>2017-03-07 10:05:13 +0300
commitb62880f7966781eb0b3b1e50f63d6aac362476d3 (patch)
tree3db7e7808baadcfbe10d329a9bfd79bfcd4b008e /drivers/gpu/drm/nouveau/nvkm/subdev/top
parent16307b5d720af3fec8d2153a68e23066e20c481f (diff)
downloadlinux-b62880f7966781eb0b3b1e50f63d6aac362476d3.tar.xz
drm/nouveau/core: add SEC2 engine
SEC2 is the name given by NVIDIA to the SEC engine post-Fermi (reasons unknown). Even though it shares the same address range as SEC, its usage is quite different and this justifies a new engine. Add this engine and make TOP use it all post-TOP devices should use this implementation and not the older SEC. Also quickly add the short gp102 implementation which will be used for falcon booting purposes. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nvkm/subdev/top')
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/top/gk104.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/top/gk104.c b/drivers/gpu/drm/nouveau/nvkm/subdev/top/gk104.c
index efac3402f9dd..fea4957291da 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/top/gk104.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/top/gk104.c
@@ -82,7 +82,7 @@ gk104_top_oneinit(struct nvkm_top *top)
case 0x0000000a: A_(MSVLD ); break;
case 0x0000000b: A_(MSENC ); break;
case 0x0000000c: A_(VIC ); break;
- case 0x0000000d: A_(SEC ); break;
+ case 0x0000000d: A_(SEC2 ); break;
case 0x0000000e: B_(NVENC ); break;
case 0x0000000f: A_(NVENC1); break;
case 0x00000010: A_(NVDEC ); break;