diff options
author | Ben Skeggs <bskeggs@redhat.com> | 2015-08-20 07:54:08 +0300 |
---|---|---|
committer | Ben Skeggs <bskeggs@redhat.com> | 2015-08-28 05:40:13 +0300 |
commit | c0e297dc61f8d4453e07afbea1fa8d0e67cd4a34 (patch) | |
tree | fbe67d9176d37af13abe20d5925112e8bdb0fe79 /drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c | |
parent | 8c1aeaa13954585e8482866457abacb5c094db35 (diff) | |
download | linux-c0e297dc61f8d4453e07afbea1fa8d0e67cd4a34.tar.xz |
drm/nouveau/sec: cosmetic changes
This is purely preparation for upcoming commits, there should be no
code changes here.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c')
-rw-r--r-- | drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c | 48 |
1 files changed, 22 insertions, 26 deletions
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c b/drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c index a598d6dbff46..1de94ec18a78 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c @@ -29,10 +29,6 @@ #include <core/enum.h> #include <engine/fifo.h> -struct g98_sec_priv { - struct nvkm_falcon base; -}; - /******************************************************************************* * Crypt object classes ******************************************************************************/ @@ -78,33 +74,33 @@ g98_sec_intr(struct nvkm_subdev *subdev) struct nvkm_fifo *fifo = nvkm_fifo(subdev); struct nvkm_engine *engine = nv_engine(subdev); struct nvkm_object *engctx; - struct g98_sec_priv *priv = (void *)subdev; - u32 disp = nv_rd32(priv, 0x08701c); - u32 stat = nv_rd32(priv, 0x087008) & disp & ~(disp >> 16); - u32 inst = nv_rd32(priv, 0x087050) & 0x3fffffff; - u32 ssta = nv_rd32(priv, 0x087040) & 0x0000ffff; - u32 addr = nv_rd32(priv, 0x087040) >> 16; + struct nvkm_falcon *sec = (void *)subdev; + u32 disp = nv_rd32(sec, 0x08701c); + u32 stat = nv_rd32(sec, 0x087008) & disp & ~(disp >> 16); + u32 inst = nv_rd32(sec, 0x087050) & 0x3fffffff; + u32 ssta = nv_rd32(sec, 0x087040) & 0x0000ffff; + u32 addr = nv_rd32(sec, 0x087040) >> 16; u32 mthd = (addr & 0x07ff) << 2; u32 subc = (addr & 0x3800) >> 11; - u32 data = nv_rd32(priv, 0x087044); + u32 data = nv_rd32(sec, 0x087044); int chid; engctx = nvkm_engctx_get(engine, inst); chid = fifo->chid(fifo, engctx); if (stat & 0x00000040) { - nv_error(priv, "DISPATCH_ERROR ["); + nv_error(sec, "DISPATCH_ERROR ["); nvkm_enum_print(g98_sec_isr_error_name, ssta); pr_cont("] ch %d [0x%010llx %s] subc %d mthd 0x%04x data 0x%08x\n", chid, (u64)inst << 12, nvkm_client_name(engctx), subc, mthd, data); - nv_wr32(priv, 0x087004, 0x00000040); + nv_wr32(sec, 0x087004, 0x00000040); stat &= ~0x00000040; } if (stat) { - nv_error(priv, "unhandled intr 0x%08x\n", stat); - nv_wr32(priv, 0x087004, stat); + nv_error(sec, "unhandled intr 0x%08x\n", stat); + nv_wr32(sec, 0x087004, stat); } nvkm_engctx_put(engctx); @@ -115,23 +111,23 @@ g98_sec_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { - struct g98_sec_priv *priv; + struct nvkm_falcon *sec; int ret; ret = nvkm_falcon_create(parent, engine, oclass, 0x087000, true, - "PSEC", "sec", &priv); - *pobject = nv_object(priv); + "PSEC", "sec", &sec); + *pobject = nv_object(sec); if (ret) return ret; - nv_subdev(priv)->unit = 0x00004000; - nv_subdev(priv)->intr = g98_sec_intr; - nv_engine(priv)->cclass = &g98_sec_cclass; - nv_engine(priv)->sclass = g98_sec_sclass; - nv_falcon(priv)->code.data = g98_psec_code; - nv_falcon(priv)->code.size = sizeof(g98_psec_code); - nv_falcon(priv)->data.data = g98_psec_data; - nv_falcon(priv)->data.size = sizeof(g98_psec_data); + nv_subdev(sec)->unit = 0x00004000; + nv_subdev(sec)->intr = g98_sec_intr; + nv_engine(sec)->cclass = &g98_sec_cclass; + nv_engine(sec)->sclass = g98_sec_sclass; + nv_falcon(sec)->code.data = g98_sec_code; + nv_falcon(sec)->code.size = sizeof(g98_sec_code); + nv_falcon(sec)->data.data = g98_sec_data; + nv_falcon(sec)->data.size = sizeof(g98_sec_data); return 0; } |