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| author | Archit Taneja <architt@codeaurora.org> | 2018-01-17 12:34:44 +0300 |
|---|---|---|
| committer | Rob Clark <robdclark@gmail.com> | 2018-02-20 18:41:21 +0300 |
| commit | c1d97083cd48a2b3f4382f0122889d1d73661b2e (patch) | |
| tree | bc46d319e601b0fff145706d4e09eba81dc0693a /drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c | |
| parent | 02f7a6ca1692ffe1012abd512b8a88ba9a925095 (diff) | |
| download | linux-c1d97083cd48a2b3f4382f0122889d1d73661b2e.tar.xz | |
drm/msm/dsi: Add byte_intf_clk
DSI6G v2.0+ blocks have a new clock input to them called
byte_intf_clk. It's rate is to be set as byte_clk / 2.
Within the clock controller (CC) subsystem, this clock is a
child/descendant of the byte_clk.
Set it up as an optional clock in the DSI host driver. Make sure
that we enable/set its rate only after we configure byte_clk.
This is required for the ancestor clocks in the CC to be
configured correctly.
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
Diffstat (limited to 'drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c')
0 files changed, 0 insertions, 0 deletions