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authorDmitry Baryshkov <dmitry.baryshkov@linaro.org>2023-03-16 19:16:29 +0300
committerDmitry Baryshkov <dmitry.baryshkov@linaro.org>2023-04-06 20:29:41 +0300
commit74fd7fda0f1ff6157ac2ff922e71b86ffab8ce23 (patch)
tree1f91c46537d0447593cd5da81f183ffda54a7cbf /drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
parent3cfcd1307af8f96420dd998c1c3fc07ce1e6d03a (diff)
downloadlinux-74fd7fda0f1ff6157ac2ff922e71b86ffab8ce23.tar.xz
drm/msm/dpu: use dpu_sw_pipe for dpu_hw_sspp callbacks
Where feasible, use dpu_sw_pipe rather than a combo of dpu_hw_sspp and multirect_index/_mode arguments. Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Tested-by: Abhinav Kumar <quic_abhinavk@quicinc.com> # sc7280 Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/527333/ Link: https://lore.kernel.org/r/20230316161653.4106395-9-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Diffstat (limited to 'drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c')
-rw-r--r--drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c73
1 files changed, 33 insertions, 40 deletions
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index 8109ad8f9d0a..e48e54064e33 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -484,23 +484,21 @@ static void _dpu_plane_set_scanout(struct drm_plane *plane,
if (ret)
DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret);
else if (pstate->pipe.sspp->ops.setup_sourceaddress) {
- trace_dpu_plane_set_scanout(pstate->pipe.sspp->idx,
- &pipe_cfg->layout,
- pstate->pipe.multirect_index);
- pstate->pipe.sspp->ops.setup_sourceaddress(pstate->pipe.sspp, pipe_cfg,
- pstate->pipe.multirect_index);
+ trace_dpu_plane_set_scanout(&pstate->pipe,
+ &pipe_cfg->layout);
+ pstate->pipe.sspp->ops.setup_sourceaddress(&pstate->pipe, pipe_cfg);
}
}
-static void _dpu_plane_setup_scaler3(struct dpu_plane *pdpu,
- struct dpu_plane_state *pstate,
+static void _dpu_plane_setup_scaler3(struct dpu_hw_sspp *pipe_hw,
uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h,
struct dpu_hw_scaler3_cfg *scale_cfg,
const struct dpu_format *fmt,
- uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v)
+ uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v,
+ unsigned int rotation)
{
uint32_t i;
- bool inline_rotation = pstate->rotation & DRM_MODE_ROTATE_90;
+ bool inline_rotation = rotation & DRM_MODE_ROTATE_90;
/*
* For inline rotation cases, scaler config is post-rotation,
@@ -539,7 +537,7 @@ static void _dpu_plane_setup_scaler3(struct dpu_plane *pdpu,
scale_cfg->src_height[i] /= chroma_subsmpl_v;
}
- if (pstate->pipe.sspp->cap->features &
+ if (pipe_hw->cap->features &
BIT(DPU_SSPP_SCALER_QSEED4)) {
scale_cfg->preload_x[i] = DPU_QSEED4_DEFAULT_PRELOAD_H;
scale_cfg->preload_y[i] = DPU_QSEED4_DEFAULT_PRELOAD_V;
@@ -636,11 +634,12 @@ static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_plane *pdpu, cons
return csc_ptr;
}
-static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu,
- struct dpu_plane_state *pstate,
+static void _dpu_plane_setup_scaler(struct dpu_sw_pipe *pipe,
const struct dpu_format *fmt, bool color_fill,
- struct dpu_hw_sspp_cfg *pipe_cfg)
+ struct dpu_hw_sspp_cfg *pipe_cfg,
+ unsigned int rotation)
{
+ struct dpu_hw_sspp *pipe_hw = pipe->sspp;
const struct drm_format_info *info = drm_format_info(fmt->base.pixel_format);
struct dpu_hw_scaler3_cfg scaler3_cfg;
struct dpu_hw_pixel_ext pixel_ext;
@@ -654,20 +653,21 @@ static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu,
/* don't chroma subsample if decimating */
/* update scaler. calculate default config for QSEED3 */
- _dpu_plane_setup_scaler3(pdpu, pstate,
+ _dpu_plane_setup_scaler3(pipe_hw,
src_width,
src_height,
dst_width,
dst_height,
&scaler3_cfg, fmt,
- info->hsub, info->vsub);
+ info->hsub, info->vsub,
+ rotation);
/* configure pixel extension based on scalar config */
_dpu_plane_setup_pixel_ext(&scaler3_cfg, &pixel_ext,
src_width, src_height, info->hsub, info->vsub);
- if (pstate->pipe.sspp->ops.setup_pe)
- pstate->pipe.sspp->ops.setup_pe(pstate->pipe.sspp,
+ if (pipe_hw->ops.setup_pe)
+ pipe_hw->ops.setup_pe(pipe_hw,
&pixel_ext);
/**
@@ -675,9 +675,9 @@ static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu,
* bypassed. Still we need to update alpha and bitwidth
* ONLY for RECT0
*/
- if (pstate->pipe.sspp->ops.setup_scaler &&
- pstate->pipe.multirect_index != DPU_SSPP_RECT_1)
- pstate->pipe.sspp->ops.setup_scaler(pstate->pipe.sspp,
+ if (pipe_hw->ops.setup_scaler &&
+ pipe->multirect_index != DPU_SSPP_RECT_1)
+ pipe_hw->ops.setup_scaler(pipe_hw,
pipe_cfg,
&scaler3_cfg);
}
@@ -707,9 +707,8 @@ static int _dpu_plane_color_fill(struct dpu_plane *pdpu,
/* update sspp */
if (fmt && pstate->pipe.sspp->ops.setup_solidfill) {
- pstate->pipe.sspp->ops.setup_solidfill(pstate->pipe.sspp,
- (color & 0xFFFFFF) | ((alpha & 0xFF) << 24),
- pstate->pipe.multirect_index);
+ pstate->pipe.sspp->ops.setup_solidfill(&pstate->pipe,
+ (color & 0xFFFFFF) | ((alpha & 0xFF) << 24));
/* override scaler/decimation if solid fill */
pipe_cfg.dst_rect = pstate->base.dst;
@@ -722,16 +721,14 @@ static int _dpu_plane_color_fill(struct dpu_plane *pdpu,
drm_rect_height(&pipe_cfg.dst_rect);
if (pstate->pipe.sspp->ops.setup_format)
- pstate->pipe.sspp->ops.setup_format(pstate->pipe.sspp,
- fmt, DPU_SSPP_SOLID_FILL,
- pstate->pipe.multirect_index);
+ pstate->pipe.sspp->ops.setup_format(&pstate->pipe,
+ fmt, DPU_SSPP_SOLID_FILL);
if (pstate->pipe.sspp->ops.setup_rects)
- pstate->pipe.sspp->ops.setup_rects(pstate->pipe.sspp,
- &pipe_cfg,
- pstate->pipe.multirect_index);
+ pstate->pipe.sspp->ops.setup_rects(&pstate->pipe,
+ &pipe_cfg);
- _dpu_plane_setup_scaler(pdpu, pstate, fmt, true, &pipe_cfg);
+ _dpu_plane_setup_scaler(&pstate->pipe, fmt, true, &pipe_cfg, pstate->rotation);
}
return 0;
@@ -1170,18 +1167,15 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
}
if (pipe->sspp->ops.setup_rects) {
- pipe->sspp->ops.setup_rects(pipe->sspp,
- &pipe_cfg,
- pipe->multirect_index);
+ pipe->sspp->ops.setup_rects(pipe,
+ &pipe_cfg);
}
- _dpu_plane_setup_scaler(pdpu, pstate, fmt, false, &pipe_cfg);
+ _dpu_plane_setup_scaler(pipe, fmt, false, &pipe_cfg, pstate->rotation);
if (pipe->sspp->ops.setup_multirect)
pipe->sspp->ops.setup_multirect(
- pipe->sspp,
- pipe->multirect_index,
- pipe->multirect_mode);
+ pipe);
if (pipe->sspp->ops.setup_format) {
unsigned int rotation = pstate->rotation;
@@ -1198,8 +1192,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
src_flags |= DPU_SSPP_ROT_90;
/* update format */
- pipe->sspp->ops.setup_format(pipe->sspp, fmt, src_flags,
- pipe->multirect_index);
+ pipe->sspp->ops.setup_format(pipe, fmt, src_flags);
if (pipe->sspp->ops.setup_cdp) {
struct dpu_hw_cdp_cfg cdp_cfg;
@@ -1215,7 +1208,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
DPU_FORMAT_IS_TILE(fmt);
cdp_cfg.preload_ahead = DPU_SSPP_CDP_PRELOAD_AHEAD_64;
- pipe->sspp->ops.setup_cdp(pipe->sspp, &cdp_cfg, pipe->multirect_index);
+ pipe->sspp->ops.setup_cdp(pipe, &cdp_cfg);
}
}