diff options
| author | Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | 2023-07-29 00:33:18 +0300 |
|---|---|---|
| committer | Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | 2023-08-02 12:37:36 +0300 |
| commit | a2e87e9ef891a0eec8de8ea8b060beaf4afd3ee2 (patch) | |
| tree | 80818632f1cede9a367c80f4d0182370a2b9d929 /drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | |
| parent | 6f410b24620914733a9d7f8d73a00d357e830080 (diff) | |
| download | linux-a2e87e9ef891a0eec8de8ea8b060beaf4afd3ee2.tar.xz | |
drm/msm/dpu: use MDSS data for programming SSPP
Switch to using data from MDSS driver to program the SSPP fetch and UBWC
configuration. As a side-effect, this also swithes the DPU driver from
DPU_HW_UBWC_VER_xx values to the UBWC_x_y enum, which reflects
the hardware register values.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/550054/
Link: https://lore.kernel.org/r/20230728213320.97309-6-dmitry.baryshkov@linaro.org
Diffstat (limited to 'drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c')
| -rw-r--r-- | drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 18 |
1 files changed, 10 insertions, 8 deletions
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c index b364cf75bb3f..f2192de93713 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c @@ -8,6 +8,8 @@ #include "dpu_hw_sspp.h" #include "dpu_kms.h" +#include "msm_mdss.h" + #include <drm/drm_file.h> #define DPU_FETCH_CONFIG_RESET_VALUE 0x00000087 @@ -270,26 +272,26 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe, DPU_REG_WRITE(c, SSPP_FETCH_CONFIG, DPU_FETCH_CONFIG_RESET_VALUE | ctx->ubwc->highest_bank_bit << 18); - switch (ctx->ubwc->ubwc_version) { - case DPU_HW_UBWC_VER_10: + switch (ctx->ubwc->ubwc_enc_version) { + case UBWC_1_0: fast_clear = fmt->alpha_enable ? BIT(31) : 0; DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, fast_clear | (ctx->ubwc->ubwc_swizzle & 0x1) | BIT(8) | (ctx->ubwc->highest_bank_bit << 4)); break; - case DPU_HW_UBWC_VER_20: + case UBWC_2_0: fast_clear = fmt->alpha_enable ? BIT(31) : 0; DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, fast_clear | (ctx->ubwc->ubwc_swizzle) | (ctx->ubwc->highest_bank_bit << 4)); break; - case DPU_HW_UBWC_VER_30: + case UBWC_3_0: DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, BIT(30) | (ctx->ubwc->ubwc_swizzle) | (ctx->ubwc->highest_bank_bit << 4)); break; - case DPU_HW_UBWC_VER_40: + case UBWC_4_0: DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, DPU_FORMAT_IS_YUV(fmt) ? 0 : BIT(30)); break; @@ -670,11 +672,11 @@ int _dpu_hw_sspp_init_debugfs(struct dpu_hw_sspp *hw_pipe, struct dpu_kms *kms, #endif struct dpu_hw_sspp *dpu_hw_sspp_init(const struct dpu_sspp_cfg *cfg, - void __iomem *addr, const struct dpu_ubwc_cfg *ubwc) + void __iomem *addr, const struct msm_mdss_data *mdss_data) { struct dpu_hw_sspp *hw_pipe; - if (!addr || !ubwc) + if (!addr) return ERR_PTR(-EINVAL); hw_pipe = kzalloc(sizeof(*hw_pipe), GFP_KERNEL); @@ -685,7 +687,7 @@ struct dpu_hw_sspp *dpu_hw_sspp_init(const struct dpu_sspp_cfg *cfg, hw_pipe->hw.log_mask = DPU_DBG_MASK_SSPP; /* Assign ops */ - hw_pipe->ubwc = ubwc; + hw_pipe->ubwc = mdss_data; hw_pipe->idx = cfg->id; hw_pipe->cap = cfg; _setup_layer_ops(hw_pipe, hw_pipe->cap->features); |