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authorJordan Crouse <jcrouse@codeaurora.org>2017-10-20 20:06:57 +0300
committerRob Clark <robdclark@gmail.com>2017-10-28 18:01:36 +0300
commitf97decac5f4c2d862e5b848694e3ffb29fc8acdd (patch)
tree1967285c12465308cd47769a43326db9506ca0d8 /drivers/gpu/drm/msm/adreno/a5xx_gpu.h
parentcd414f3d931687eb1ebeb87533d85537e315f195 (diff)
downloadlinux-f97decac5f4c2d862e5b848694e3ffb29fc8acdd.tar.xz
drm/msm: Support multiple ringbuffers
Add the infrastructure to support the idea of multiple ringbuffers. Assign each ringbuffer an id and use that as an index for the various ring specific operations. The biggest delta is to support legacy fences. Each fence gets its own sequence number but the legacy functions expect to use a unique integer. To handle this we return a unique identifier for each submission but map it to a specific ring/sequence under the covers. Newer users use a dma_fence pointer anyway so they don't care about the actual sequence ID or ring. The actual mechanics for multiple ringbuffers are very target specific so this code just allows for the possibility but still only defines one ringbuffer for each target family. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
Diffstat (limited to 'drivers/gpu/drm/msm/adreno/a5xx_gpu.h')
-rw-r--r--drivers/gpu/drm/msm/adreno/a5xx_gpu.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.h b/drivers/gpu/drm/msm/adreno/a5xx_gpu.h
index e94451685bf8..44db48d86202 100644
--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.h
@@ -55,7 +55,7 @@ static inline int spin_usecs(struct msm_gpu *gpu, uint32_t usecs,
return -ETIMEDOUT;
}
-bool a5xx_idle(struct msm_gpu *gpu);
+bool a5xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
void a5xx_set_hwcg(struct msm_gpu *gpu, bool state);
#endif /* __A5XX_GPU_H__ */