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| author | Chris Wilson <chris@chris-wilson.co.uk> | 2018-06-15 12:31:37 +0300 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2018-06-15 21:50:37 +0300 |
| commit | b2209e62a4507f6649233eaf0675de3ad86bd868 (patch) | |
| tree | ffcce16b9d59946b29fc416da81237ccc783b217 /drivers/gpu/drm/i915/intel_lrc.c | |
| parent | 042ed2dbe5b294e6c225e12d380062ee6adb3ac0 (diff) | |
| download | linux-b2209e62a4507f6649233eaf0675de3ad86bd868.tar.xz | |
drm/i915/execlists: Reset the CSB head tracking on reset/sanitization
We can avoid the mmio read of the CSB pointers after reset based on the
knowledge that the HW always start writing at entry 0 in the CSB buffer.
We need to reset our CSB head tracking after GPU reset (and on
sanitization after resume) so that we are expecting to read from entry
0, hence we reset our head tracking back to the entry before (the last
entry in the ring).
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180615093137.14270-2-chris@chris-wilson.co.uk
Diffstat (limited to 'drivers/gpu/drm/i915/intel_lrc.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_lrc.c | 15 |
1 files changed, 6 insertions, 9 deletions
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 8d56bcb00979..50e141ca1f7a 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -971,22 +971,19 @@ static void process_csb(struct intel_engine_cs *engine) &engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX]; unsigned int head, tail; - if (unlikely(execlists->csb_use_mmio)) { - buf = (u32 * __force) - (i915->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0))); - execlists->csb_head = -1; /* force mmio read of CSB */ - } - /* Clear before reading to catch new interrupts */ clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted); smp_mb__after_atomic(); - if (unlikely(execlists->csb_head == -1)) { /* after a reset */ + if (unlikely(execlists->csb_use_mmio)) { if (!fw) { intel_uncore_forcewake_get(i915, execlists->fw_domains); fw = true; } + buf = (u32 * __force) + (i915->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0))); + head = readl(i915->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine))); tail = GEN8_CSB_WRITE_PTR(head); head = GEN8_CSB_READ_PTR(head); @@ -1961,7 +1958,7 @@ static void execlists_reset(struct intel_engine_cs *engine, spin_unlock(&engine->timeline.lock); /* Following the reset, we need to reload the CSB read/write pointers */ - engine->execlists.csb_head = -1; + engine->execlists.csb_head = GEN8_CSB_ENTRIES - 1; local_irq_restore(flags); @@ -2469,7 +2466,7 @@ static int logical_ring_init(struct intel_engine_cs *engine) upper_32_bits(ce->lrc_desc); } - engine->execlists.csb_head = -1; + engine->execlists.csb_head = GEN8_CSB_ENTRIES - 1; return 0; |