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| author | Lionel Landwerlin <lionel.g.landwerlin@intel.com> | 2022-10-27 01:21:01 +0300 |
|---|---|---|
| committer | John Harrison <John.C.Harrison@Intel.com> | 2022-10-27 22:37:02 +0300 |
| commit | 0fa9349dda030fa847b36f880a5eea25c3202b66 (patch) | |
| tree | d25bb9391bd35c3e61bee0725f4bafcb79b6bdaf /drivers/gpu/drm/i915/i915_pci.c | |
| parent | 01e7427467857861d1aaa7cd05598dfcb631c5b5 (diff) | |
| download | linux-0fa9349dda030fa847b36f880a5eea25c3202b66.tar.xz | |
drm/i915/perf: complete programming whitelisting for XEHPSDV
We have an additional register to select which slices contribute to
OAG/OAG counter increments.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221026222102.5526-16-umesh.nerlige.ramappa@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_pci.c')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_pci.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 7b751bf4be21..6b22fb506aa9 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -1024,6 +1024,7 @@ static const struct intel_device_info adl_p_info = { .has_logical_ring_elsq = 1, \ .has_mslice_steering = 1, \ .has_oa_bpc_reporting = 1, \ + .has_oa_slice_contrib_limits = 1, \ .has_rc6 = 1, \ .has_reset_engine = 1, \ .has_rps = 1, \ |