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| author | Chris Wilson <chris@chris-wilson.co.uk> | 2019-08-30 20:59:59 +0300 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2019-08-30 22:49:56 +0300 |
| commit | 0b718ba1e884f64dce27c19311dd2859b87e56b9 (patch) | |
| tree | 22346bb09262c213864897e1c872830a6c88bc4d /drivers/gpu/drm/i915/i915_pci.c | |
| parent | 3dc007fe9b2b256d2779bb9e9a0d372eb1d90643 (diff) | |
| download | linux-0b718ba1e884f64dce27c19311dd2859b87e56b9.tar.xz | |
drm/i915/gtt: Downgrade Cherryview back to aliasing-ppgtt
With the upcoming change in timing (dramatically reducing the latency
between manipulating the ppGTT and execution), no amount of tweaking
could save Cherryview, it would always fail to invalidate its TLB.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Matthew Auld <matthew.auld@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190830180000.24608-2-chris@chris-wilson.co.uk
Diffstat (limited to 'drivers/gpu/drm/i915/i915_pci.c')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_pci.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 18212c39a9ba..fbe98a2db88e 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -570,7 +570,7 @@ static const struct intel_device_info intel_cherryview_info = { .has_rps = true, .has_logical_ring_contexts = 1, .display.has_gmch = 1, - .ppgtt_type = INTEL_PPGTT_FULL, + .ppgtt_type = INTEL_PPGTT_ALIASING, .ppgtt_size = 32, .has_reset_engine = 1, .has_snoop = true, |