diff options
| author | Imre Deak <imre.deak@intel.com> | 2017-07-11 23:42:35 +0300 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2017-07-27 10:38:53 +0300 |
| commit | b2891eb2531e5e0d251febd0a395d758111790d4 (patch) | |
| tree | 122b5d0206a9ce94ffd9a2b5935fadc5371a20bf /drivers/gpu/drm/i915/gvt/display.c | |
| parent | 76347c04d879267839337adc2aea6136b58c2ca7 (diff) | |
| download | linux-b2891eb2531e5e0d251febd0a395d758111790d4.tar.xz | |
drm/i915/hsw+: Add has_fuses power well attribute
The pattern of a power well backing a set of fuses whose initialization
we need to wait for during power well enabling is common to all GEN9+
platforms. Adding support for this to the HSW power well enable helper
allows us to use the HSW/BDW power well code for GEN9+ as well in a
follow-up patch.
v2:
- Use an enum for power gates instead of raw numbers. (Ville)
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170711204236.5618-6-imre.deak@intel.com
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/gvt/display.c')
| -rw-r--r-- | drivers/gpu/drm/i915/gvt/display.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c index 2deb05f618fb..24cc4b012e93 100644 --- a/drivers/gpu/drm/i915/gvt/display.c +++ b/drivers/gpu/drm/i915/gvt/display.c @@ -178,9 +178,9 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) SDE_PORTE_HOTPLUG_SPT); vgpu_vreg(vgpu, SKL_FUSE_STATUS) |= SKL_FUSE_DOWNLOAD_STATUS | - SKL_FUSE_PG0_DIST_STATUS | - SKL_FUSE_PG1_DIST_STATUS | - SKL_FUSE_PG2_DIST_STATUS; + SKL_FUSE_PG_DIST_STATUS(SKL_PG0) | + SKL_FUSE_PG_DIST_STATUS(SKL_PG1) | + SKL_FUSE_PG_DIST_STATUS(SKL_PG2); vgpu_vreg(vgpu, LCPLL1_CTL) |= LCPLL_PLL_ENABLE | LCPLL_PLL_LOCK; |