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| author | Tvrtko Ursulin <tvrtko.ursulin@intel.com> | 2021-07-22 01:30:30 +0300 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2021-07-23 05:15:06 +0300 |
| commit | eea97e42f48bff0706b620730799b5057c9caf90 (patch) | |
| tree | 9c80265f212d7fb80dfd5eb062d2954ebea1d594 /drivers/gpu/drm/i915/gem/i915_gem_shrinker.c | |
| parent | 265b5ee0d32bbb3439bfcce8a7b60ec2f4c0acc5 (diff) | |
| download | linux-eea97e42f48bff0706b620730799b5057c9caf90.tar.xz | |
drm/i915/xehp: VDBOX/VEBOX fusing registers are enable-based
On Xe_HP the fusing register is renamed and changed to have the "enable"
semantics, but otherwise remains compatible (mmio address, bitmask
ranges) with older platforms.
To simplify things we do not add a new register definition but just stop
inverting the fusing masks before processing them.
Bspec: 52615
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210721223043.834562-6-matthew.d.roper@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/gem/i915_gem_shrinker.c')
0 files changed, 0 insertions, 0 deletions