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authorVille Syrjälä <ville.syrjala@linux.intel.com>2025-01-22 18:17:53 +0300
committerVille Syrjälä <ville.syrjala@linux.intel.com>2025-02-06 16:35:44 +0300
commit44a34dec43e8f214913e16204525d7253acc1891 (patch)
treed553fdde60a33693b209c49651168802d2d399f9 /drivers/gpu/drm/i915/display/intel_fbdev.c
parent2ffa4878512d429eecffe4ef786cbf102a8b8165 (diff)
downloadlinux-44a34dec43e8f214913e16204525d7253acc1891.tar.xz
drm/i915: Calculate the VT-d guard size in the display code
Currently i915_gem_object_pin_to_display_plane() uses i915_gem_object_get_tile_row_size() to calculate the tile row size for the VT-d guard w/a. That's not really proper since i915_gem_object_get_tile_row_size() only works for fenced BOs, nor does it take rotation into account. Remedy the situation by calculating the VT-d guard size in the display code where we have more information readily available. Although the default guard size (168 PTEs now) should cover the more typical fb size use cases anyway, and only very large Y/Yf-tiled framebuffers might have tile row size that exceeds it. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250122151755.6928-4-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_fbdev.c')
-rw-r--r--drivers/gpu/drm/i915/display/intel_fbdev.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c b/drivers/gpu/drm/i915/display/intel_fbdev.c
index 6c0808133397..833cded53d37 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
@@ -228,6 +228,8 @@ static int intelfb_create(struct drm_fb_helper *helper,
*/
vma = intel_fb_pin_to_ggtt(&fb->base, &view,
fb->min_alignment, 0,
+ intel_fb_view_vtd_guard(&fb->base, &fb->normal_view,
+ DRM_MODE_ROTATE_0),
false, &flags);
if (IS_ERR(vma)) {
ret = PTR_ERR(vma);