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authorVille Syrjälä <ville.syrjala@linux.intel.com>2023-03-29 16:49:58 +0300
committerVille Syrjälä <ville.syrjala@linux.intel.com>2023-04-11 09:33:43 +0300
commit01c2be8e1b97ee4891d1e1ffb7758897d441bb3c (patch)
treeae9dec4cb1dc315e3357ff547dd3a21402194cb3 /drivers/gpu/drm/i915/display/intel_display.c
parente006df050606785aa7d04cd47f913d9c6ce4669d (diff)
downloadlinux-01c2be8e1b97ee4891d1e1ffb7758897d441bb3c.tar.xz
drm/i915: Add hardware csc readout for ilk+
Read out the pipe/output csc matrices on ilk+ and stash the results (in the hardware specific format) into the appropriate place in the crtc state. Note that on skl/glk/icl the pipe csc unit suffers from an issue where *reads* of the coefficient/offset registers also disarm the double buffer update (if currently armed via CSC_MODE write). So it's rather important that the readout only happens after the csc registers have been latched. Fortunately the state checker only runs after the start of vblank where the latching happens. And on skl/glk the DMC + CSC register read has the potential to corrupt the latched CSC register values, so let's add a comment reminding us that the DC states should remain off until the readout has been completed. TODO: maybe we could somehow check to make sure PSR has in fact latched the new register values already, and that DC states have been off all along? Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230329135002.3096-9-ville.syrjala@linux.intel.com Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_display.c')
-rw-r--r--drivers/gpu/drm/i915/display/intel_display.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 010ee793e1ff..270658e93141 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7313,6 +7313,12 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
* 7. New _arm() registers are finally written
* 8. Hardware finally latches a complete set of new
* register values, and subsequent frames will be OK again
+ *
+ * Also note that due to the pipe CSC hardware issues on
+ * SKL/GLK DC states must remain off until the pipe CSC
+ * state readout has happened. Otherwise we risk corrupting
+ * the CSC latched register values with the readout (see
+ * skl_read_csc() and skl_color_commit_noarm()).
*/
wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DC_OFF);