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| author | Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> | 2021-02-08 15:27:12 +0300 |
|---|---|---|
| committer | Joerg Roedel <jroedel@suse.de> | 2021-02-12 13:46:45 +0300 |
| commit | 6778ff5b21bd8e78c8bd547fd66437cf2657fd9b (patch) | |
| tree | 0d0287f292266ac12606d51a5d17ca3dbc44f6d4 /drivers/gpu/drm/drm_dp_mst_topology_internal.h | |
| parent | 89c9a09cb9f6e0a7df77f9c9bafd3c96148bf0d5 (diff) | |
| download | linux-6778ff5b21bd8e78c8bd547fd66437cf2657fd9b.tar.xz | |
iommu/amd: Fix performance counter initialization
Certain AMD platforms enable power gating feature for IOMMU PMC,
which prevents the IOMMU driver from updating the counter while
trying to validate the PMC functionality in the init_iommu_perf_ctr().
This results in disabling PMC support and the following error message:
"AMD-Vi: Unable to read/write to IOMMU perf counter"
To workaround this issue, disable power gating temporarily by programming
the counter source to non-zero value while validating the counter,
and restore the prior state afterward.
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Tested-by: Tj (Elloe Linux) <ml.linux@elloe.vision>
Link: https://lore.kernel.org/r/20210208122712.5048-1-suravee.suthikulpanit@amd.com
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=201753
Signed-off-by: Joerg Roedel <jroedel@suse.de>
Diffstat (limited to 'drivers/gpu/drm/drm_dp_mst_topology_internal.h')
0 files changed, 0 insertions, 0 deletions