diff options
| author | Yongqiang Sun <yongqiang.sun@amd.com> | 2018-02-23 00:50:39 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2018-03-14 23:08:43 +0300 |
| commit | 623a7e96cd73a46d15f64b1c5e1f4ea3548271f2 (patch) | |
| tree | 1080cc9ffe9e6e2f3acf2c1111978412c22bda52 /drivers/gpu/drm/amd/display/dc | |
| parent | 5e3e341cee51a755b81a660806bfcad3fdcfc906 (diff) | |
| download | linux-623a7e96cd73a46d15f64b1c5e1f4ea3548271f2.tar.xz | |
drm/amd/display: Remove 300Mhz minimum disp clk limit.
300Mhz disp clk limit was a workaround that was fixed in SMU and is no
longer needed.
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/core/dc.c | 5 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 3 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 2 |
3 files changed, 5 insertions, 5 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index e72fdb5697fc..fa402291a921 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -803,6 +803,8 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c if (!dcb->funcs->is_accelerated_mode(dcb)) dc->hwss.enable_accelerated_mode(dc, context); + dc->hwss.set_bandwidth(dc, context, false); + /* re-program planes for existing stream, in case we need to * free up plane resource for later use */ @@ -869,6 +871,9 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c context->streams[i]->timing.pix_clk_khz); } + /* pplib is notified if disp_num changed */ + dc->hwss.set_bandwidth(dc, context, true); + dc_enable_stereo(dc, context, dc_streams, context->stream_count); dc_release_state(dc->current_state); diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index c2041a63cccd..ca0484894084 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -2106,9 +2106,6 @@ enum dc_status dce110_apply_ctx_to_hw( return status; } - /* pplib is notified if disp_num changed */ - dc->hwss.set_bandwidth(dc, context, true); - /* to save power */ apply_min_clocks(dc, context, &clocks_state, false); diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index 617aa8ca0156..e7406c74dd48 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -440,8 +440,6 @@ static const struct dc_debug debug_defaults_drv = { .timing_trace = false, .clock_trace = true, - .min_disp_clk_khz = 300000, - .disable_pplib_clock_request = true, .disable_pplib_wm_range = false, .pplib_wm_report_mode = WM_REPORT_DEFAULT, |