drm/amd/display: move public dc link function implementation to dc_link_exports

[why]
Link is a subcomponent in dc. DM should be aware of dc link structure
as one of the abstracted objects maintained by dc. However it should
have no idea of the existence of a link component in dc dedicated to
maintain the states of dc link structure. As such we are moving link interfaces
out of dc_link.h and directly added to dc.h. We are grandually fading out
the explicit inclusion of dc_link header and eventually delete it.

On dc side, since link is a subcomponent behind dc interfaces, it is not
a good idea to implement dc interfaces in each individual subcomponent
of link which is already a subcomponent of dc. So we are decoupling it
by implementing a dc_link_exports in dc. This file will be a thin
translation layer that breaks the dependency so link is able to make
interface changes without breaking DM.

Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

6 files changed, 22 insertions, 63 deletions

diff --git a/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c b/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c
index ee290ec247de..942300e0bd92 100644
--- a/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c
+++ b/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c
@@ -23,6 +23,7 @@
  *
  */
 #include "link_dp_cts.h"
+#include "link/link_resource.h"
 #include "link/protocols/link_dpcd.h"
 #include "link/protocols/link_dp_training.h"
 #include "link/protocols/link_dp_phy.h"
@@ -955,7 +956,7 @@ void dc_link_set_drive_settings(struct dc *dc,
 	if (i >= dc->link_count)
 		ASSERT_CRITICAL(false);
 
-	dc_link_get_cur_link_res(link, &link_res);
+	link_get_cur_link_res(link, &link_res);
 	dp_set_drive_settings(dc->links[i], &link_res, lt_settings);
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/link/link_detection.c b/drivers/gpu/drm/amd/display/dc/link/link_detection.c
index 29cdb61d66c8..38216c789d77 100644
--- a/drivers/gpu/drm/amd/display/dc/link/link_detection.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_detection.c
@@ -714,7 +714,7 @@ static bool discover_dp_mst_topology(struct dc_link *link, enum dc_detect_reason
 	return link->type == dc_connection_mst_branch;
 }
 
-static bool reset_cur_dp_mst_topology(struct dc_link *link)
+bool link_reset_cur_dp_mst_topology(struct dc_link *link)
 {
 	DC_LOGGER_INIT(link->ctx->logger);
 
@@ -725,10 +725,6 @@ static bool reset_cur_dp_mst_topology(struct dc_link *link)
 	return dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
 }
 
-bool dc_link_reset_cur_dp_mst_topology(struct dc_link *link)
-{
-	return reset_cur_dp_mst_topology(link);
-}
 static bool should_prepare_phy_clocks_for_link_verification(const struct dc *dc,
 		enum dc_detect_reason reason)
 {
@@ -1199,7 +1195,7 @@ static bool detect_link_and_local_sink(struct dc_link *link,
  * Does not detect downstream devices, such as MST sinks
  * or display connected through active dongles
  */
-bool dc_link_detect_connection_type(struct dc_link *link, enum dc_connection_type *type)
+bool link_detect_connection_type(struct dc_link *link, enum dc_connection_type *type)
 {
 	uint32_t is_hpd_high = 0;
 
@@ -1242,7 +1238,7 @@ hpd_gpio_failure:
 	return false;
 }
 
-bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
+bool link_detect(struct dc_link *link, enum dc_detect_reason reason)
 {
 	bool is_local_sink_detect_success;
 	bool is_delegated_to_mst_top_mgr = false;
@@ -1261,18 +1257,18 @@ bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
 	if (is_local_sink_detect_success &&
 			pre_link_type == dc_connection_mst_branch &&
 			link->type != dc_connection_mst_branch)
-		is_delegated_to_mst_top_mgr = reset_cur_dp_mst_topology(link);
+		is_delegated_to_mst_top_mgr = link_reset_cur_dp_mst_topology(link);
 
 	return is_local_sink_detect_success && !is_delegated_to_mst_top_mgr;
 }
 
-void dc_link_clear_dprx_states(struct dc_link *link)
+void link_clear_dprx_states(struct dc_link *link)
 {
 	memset(&link->dprx_states, 0, sizeof(link->dprx_states));
 }
 #if defined(CONFIG_DRM_AMD_DC_HDCP)
 
-bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal)
+bool link_is_hdcp14(struct dc_link *link, enum signal_type signal)
 {
 	bool ret = false;
 
@@ -1296,7 +1292,7 @@ bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal)
 	return ret;
 }
 
-bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal)
+bool link_is_hdcp22(struct dc_link *link, enum signal_type signal)
 {
 	bool ret = false;
 
@@ -1320,7 +1316,7 @@ bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal)
 }
 #endif // CONFIG_DRM_AMD_DC_HDCP
 
-const struct dc_link_status *dc_link_get_status(const struct dc_link *link)
+const struct dc_link_status *link_get_status(const struct dc_link *link)
 {
 	return &link->link_status;
 }
diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
index 026683ce24a4..257e1c3ba00a 100644
--- a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
@@ -958,11 +958,6 @@ out:
 	return result;
 }
 
-bool dc_link_update_dsc_config(struct pipe_ctx *pipe_ctx)
-{
-	return link_update_dsc_config(pipe_ctx);
-}
-
 bool link_update_dsc_config(struct pipe_ctx *pipe_ctx)
 {
 	struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;
diff --git a/drivers/gpu/drm/amd/display/dc/link/link_resource.c b/drivers/gpu/drm/amd/display/dc/link/link_resource.c
index 0027a7206073..bd42bb273c0c 100644
--- a/drivers/gpu/drm/amd/display/dc/link/link_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_resource.c
@@ -29,7 +29,7 @@
 #include "link_resource.h"
 #include "protocols/link_dp_capability.h"
 
-void dc_link_get_cur_link_res(const struct dc_link *link,
+void link_get_cur_link_res(const struct dc_link *link,
 		struct link_resource *link_res)
 {
 	int i;
@@ -49,24 +49,7 @@ void dc_link_get_cur_link_res(const struct dc_link *link,
 
 }
 
-/**
- * dc_get_cur_link_res_map() - take a snapshot of current link resource allocation state
- * @dc: pointer to dc of the dm calling this
- * @map: a dc link resource snapshot defined internally to dc.
- *
- * DM needs to capture a snapshot of current link resource allocation mapping
- * and store it in its persistent storage.
- *
- * Some of the link resource is using first come first serve policy.
- * The allocation mapping depends on original hotplug order. This information
- * is lost after driver is loaded next time. The snapshot is used in order to
- * restore link resource to its previous state so user will get consistent
- * link capability allocation across reboot.
- *
- * Return: none (void function)
- *
- */
-void dc_get_cur_link_res_map(const struct dc *dc, uint32_t *map)
+void link_get_cur_res_map(const struct dc *dc, uint32_t *map)
 {
 	struct dc_link *link;
 	uint32_t i;
@@ -89,25 +72,7 @@ void dc_get_cur_link_res_map(const struct dc *dc, uint32_t *map)
 	}
 }
 
-/**
- * dc_restore_link_res_map() - restore link resource allocation state from a snapshot
- * @dc: pointer to dc of the dm calling this
- * @map: a dc link resource snapshot defined internally to dc.
- *
- * DM needs to call this function after initial link detection on boot and
- * before first commit streams to restore link resource allocation state
- * from previous boot session.
- *
- * Some of the link resource is using first come first serve policy.
- * The allocation mapping depends on original hotplug order. This information
- * is lost after driver is loaded next time. The snapshot is used in order to
- * restore link resource to its previous state so user will get consistent
- * link capability allocation across reboot.
- *
- * Return: none (void function)
- *
- */
-void dc_restore_link_res_map(const struct dc *dc, uint32_t *map)
+void link_restore_res_map(const struct dc *dc, uint32_t *map)
 {
 	struct dc_link *link;
 	uint32_t i;
diff --git a/drivers/gpu/drm/amd/display/dc/link/link_resource.h b/drivers/gpu/drm/amd/display/dc/link/link_resource.h
index fb01b3caf5a4..45554d30adf0 100644
--- a/drivers/gpu/drm/amd/display/dc/link/link_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/link/link_resource.h
@@ -25,5 +25,7 @@
 #ifndef __LINK_RESOURCE_H__
 #define __LINK_RESOURCE_H__
 #include "link.h"
+void link_get_cur_link_res(const struct dc_link *link,
+		struct link_resource *link_res);
 
 #endif /* __LINK_RESOURCE_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/link/link_validation.c b/drivers/gpu/drm/amd/display/dc/link/link_validation.c
index 8ddebf3bdd46..d4f6ee6ca948 100644
--- a/drivers/gpu/drm/amd/display/dc/link/link_validation.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_validation.c
@@ -218,20 +218,20 @@ static bool dp_active_dongle_validate_timing(
 	return true;
 }
 
-uint32_t dc_link_bandwidth_kbps(
+uint32_t dp_link_bandwidth_kbps(
 	const struct dc_link *link,
-	const struct dc_link_settings *link_setting)
+	const struct dc_link_settings *link_settings)
 {
 	uint32_t total_data_bw_efficiency_x10000 = 0;
 	uint32_t link_rate_per_lane_kbps = 0;
 
-	switch (link_dp_get_encoding_format(link_setting)) {
+	switch (link_dp_get_encoding_format(link_settings)) {
 	case DP_8b_10b_ENCODING:
 		/* For 8b/10b encoding:
 		 * link rate is defined in the unit of LINK_RATE_REF_FREQ_IN_KHZ per DP byte per lane.
 		 * data bandwidth efficiency is 80% with additional 3% overhead if FEC is supported.
 		 */
-		link_rate_per_lane_kbps = link_setting->link_rate * LINK_RATE_REF_FREQ_IN_KHZ * BITS_PER_DP_BYTE;
+		link_rate_per_lane_kbps = link_settings->link_rate * LINK_RATE_REF_FREQ_IN_KHZ * BITS_PER_DP_BYTE;
 		total_data_bw_efficiency_x10000 = DATA_EFFICIENCY_8b_10b_x10000;
 		if (dc_link_should_enable_fec(link)) {
 			total_data_bw_efficiency_x10000 /= 100;
@@ -243,7 +243,7 @@ uint32_t dc_link_bandwidth_kbps(
 		 * link rate is defined in the unit of 10mbps per lane.
 		 * total data bandwidth efficiency is always 96.71%.
 		 */
-		link_rate_per_lane_kbps = link_setting->link_rate * 10000;
+		link_rate_per_lane_kbps = link_settings->link_rate * 10000;
 		total_data_bw_efficiency_x10000 = DATA_EFFICIENCY_128b_132b_x10000;
 		break;
 	default:
@@ -251,10 +251,10 @@ uint32_t dc_link_bandwidth_kbps(
 	}
 
 	/* overall effective link bandwidth = link rate per lane * lane count * total data bandwidth efficiency */
-	return link_rate_per_lane_kbps * link_setting->lane_count / 10000 * total_data_bw_efficiency_x10000;
+	return link_rate_per_lane_kbps * link_settings->lane_count / 10000 * total_data_bw_efficiency_x10000;
 }
 
-uint32_t dc_bandwidth_in_kbps_from_timing(
+uint32_t link_timing_bandwidth_kbps(
 	const struct dc_crtc_timing *timing)
 {
 	uint32_t bits_per_channel = 0;