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| author | Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> | 2020-04-22 20:29:08 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2020-05-28 21:00:48 +0300 |
| commit | 1c994f2deff1897d530441f62549f7a3a3508cda (patch) | |
| tree | 239c1dc328e40fdac4f769bbe3af8cdb25b51bc4 /drivers/gpu/drm/amd/display/dc/dml/dcn21 | |
| parent | fe5932964dffcaa1e6067cf3ea4d7f21cc242c66 (diff) | |
| download | linux-1c994f2deff1897d530441f62549f7a3a3508cda.tar.xz | |
drm/amd/display: update dml interfaces and variables
Preparation for new asic support.
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dml/dcn21')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c | 36 |
1 files changed, 1 insertions, 35 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c index 90a5fefef05b..edd41d358291 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c @@ -936,11 +936,6 @@ static void dml_rq_dlg_get_dlg_params( double refcyc_per_req_delivery_c; unsigned int full_recout_width; - double xfc_transfer_delay; - double xfc_precharge_delay; - double xfc_remote_surface_flip_latency; - double xfc_dst_y_delta_drq_limit; - double xfc_prefetch_margin; double refcyc_per_req_delivery_pre_cur0; double refcyc_per_req_delivery_cur0; double refcyc_per_req_delivery_pre_cur1; @@ -1412,25 +1407,6 @@ static void dml_rq_dlg_get_dlg_params( ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13)); } - // XFC - xfc_transfer_delay = get_xfc_transfer_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); - xfc_precharge_delay = get_xfc_precharge_delay( - mode_lib, - e2e_pipe_param, - num_pipes, - pipe_idx); - xfc_remote_surface_flip_latency = get_xfc_remote_surface_flip_latency( - mode_lib, - e2e_pipe_param, - num_pipes, - pipe_idx); - xfc_dst_y_delta_drq_limit = xfc_remote_surface_flip_latency; - xfc_prefetch_margin = get_xfc_prefetch_margin( - mode_lib, - e2e_pipe_param, - num_pipes, - pipe_idx); - // TTU - Cursor refcyc_per_req_delivery_pre_cur0 = 0.0; refcyc_per_req_delivery_cur0 = 0.0; @@ -1621,17 +1597,7 @@ static void dml_rq_dlg_get_dlg_params( disp_dlg_regs->chunk_hdl_adjust_cur1 = 3; disp_dlg_regs->dst_y_offset_cur1 = 0; - disp_dlg_regs->xfc_reg_transfer_delay = xfc_transfer_delay; - disp_dlg_regs->xfc_reg_precharge_delay = xfc_precharge_delay; - disp_dlg_regs->xfc_reg_remote_surface_flip_latency = xfc_remote_surface_flip_latency; - disp_dlg_regs->xfc_reg_prefetch_margin = dml_ceil( - xfc_prefetch_margin * refclk_freq_in_mhz, 1); - - // slave has to have this value also set to off - if (src->xfc_enable && !src->xfc_slave) - disp_dlg_regs->dst_y_delta_drq_limit = dml_ceil(xfc_dst_y_delta_drq_limit, 1); - else - disp_dlg_regs->dst_y_delta_drq_limit = 0x7fff; // off + disp_dlg_regs->dst_y_delta_drq_limit = 0x7fff; // off disp_ttu_regs->refcyc_per_req_delivery_pre_l = (unsigned int) (refcyc_per_req_delivery_pre_l * dml_pow(2, 10)); |