Merge tag 'drm-next-2023-07-07' of git://anongit.freedesktop.org/drm/drm

Pull drm fixes from Dave Airlie:
 "Lots of fixes, mostly i915 and amdgpu. It's two weeks of i915, and I
  think three weeks of amdgpu.

  fbdev:
   - Fix module infos on sparc

  panel:
   - Fix mode on Starry-ili9882t

  i915:
   - Allow DC states along with PW2 only for PWB functionality [adlp+]
   - Fix SSC selection for MPLLA [mtl]
   - Use hw.adjusted mode when calculating io/fast wake times [psr]
   - Apply min softlimit correctly [guc/slpc]
   - Assign correct hdcp content type [hdcp]
   - Add missing forward declarations/includes to display power headers
   - Fix BDW PSR AUX CH data register offsets [psr]
   - Use mock device info for creating mock device

  amdgpu:
   - Misc cleanups
   - GFX 9.4.3 fixes
   - DEBUGFS build fix
   - Fix LPDDR5 reporting
   - ASPM fixes
   - DCN 3.1.4 fixes
   - DP MST fixes
   - DCN 3.2.x fixes
   - Display PSR TCON fixes
   - SMU 13.x fixes
   - RAS fixes
   - Vega12/20 SMU fixes
   - PSP flashing cleanup
   - GFX9 MCBP fixes
   - SR-IOV fixes
   - GPUVM clear mappings fix for always valid BOs
   - Add FAMS quirk for problematic monitor
   - Fix possible UAF
   - Better handle monentary temperature fluctuations
   - SDMA 4.4.2 fixes
   - Fencing fix"

* tag 'drm-next-2023-07-07' of git://anongit.freedesktop.org/drm/drm: (83 commits)
  drm/i915: use mock device info for creating mock device
  drm/i915/psr: Fix BDW PSR AUX CH data register offsets
  drm/amdgpu: Fix potential fence use-after-free v2
  drm/amd/pm: avoid unintentional shutdown due to temperature momentary fluctuation
  drm/amd/pm: expose swctf threshold setting for legacy powerplay
  drm/amd/display: 3.2.241
  drm/amd/display: Take full update path if number of planes changed
  drm/amd/display: Create debugging mechanism for Gaming FAMS
  drm/amd/display: Add monitor specific edid quirk
  drm/amd/display: For new fast update path, loop through each surface
  drm/amd/display: Remove Phantom Pipe Check When Calculating K1 and K2
  drm/amd/display: Limit new fast update path to addr and gamma / color
  drm/amd/display: Fix the delta clamping for shaper LUT
  drm/amdgpu: Keep non-psp path for partition switch
  drm/amd/display: program DPP shaper and 3D LUT if updated
  Revert "drm/amd/display: edp do not add non-edid timings"
  drm/amdgpu: share drm device for pci amdgpu device with 1st partition device
  drm/amd/pm: Add GFX v9.4.3 unique id to sysfs
  drm/amd/pm: Enable pp_feature attribute
  drm/amdgpu/vcn: Need to unpause dpg before stop dpg
  ...

1 files changed, 7 insertions, 23 deletions

diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c
index 7a43f8868500..4d2820ffe468 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c
@@ -337,13 +337,14 @@ void dcn314_enable_power_gating_plane(struct dce_hwseq *hws, bool enable)
 		REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
 }
 
-void dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div)
+unsigned int dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div)
 {
 	struct dc_stream_state *stream = pipe_ctx->stream;
+	unsigned int odm_combine_factor = 0;
 	bool two_pix_per_container = false;
 
 	two_pix_per_container = optc2_is_two_pixels_per_containter(&stream->timing);
-	get_odm_config(pipe_ctx, NULL);
+	odm_combine_factor = get_odm_config(pipe_ctx, NULL);
 
 	if (stream->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
 		*k1_div = PIXEL_RATE_DIV_BY_1;
@@ -361,11 +362,15 @@ void dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int
 		} else {
 			*k1_div = PIXEL_RATE_DIV_BY_1;
 			*k2_div = PIXEL_RATE_DIV_BY_4;
+			if (odm_combine_factor == 2)
+				*k2_div = PIXEL_RATE_DIV_BY_2;
 		}
 	}
 
 	if ((*k1_div == PIXEL_RATE_DIV_NA) && (*k2_div == PIXEL_RATE_DIV_NA))
 		ASSERT(false);
+
+	return odm_combine_factor;
 }
 
 void dcn314_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx)
@@ -424,27 +429,6 @@ void dcn314_dpp_root_clock_control(struct dce_hwseq *hws, unsigned int dpp_inst,
 			hws->ctx->dc->res_pool->dccg, dpp_inst, clock_on);
 }
 
-void dcn314_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on)
-{
-	struct dc_context *ctx = hws->ctx;
-	union dmub_rb_cmd cmd;
-
-	if (hws->ctx->dc->debug.disable_hubp_power_gate)
-		return;
-
-	PERF_TRACE();
-
-	memset(&cmd, 0, sizeof(cmd));
-	cmd.domain_control.header.type = DMUB_CMD__VBIOS;
-	cmd.domain_control.header.sub_type = DMUB_CMD__VBIOS_DOMAIN_CONTROL;
-	cmd.domain_control.header.payload_bytes = sizeof(cmd.domain_control.data);
-	cmd.domain_control.data.inst = hubp_inst;
-	cmd.domain_control.data.power_gate = !power_on;
-
-	dm_execute_dmub_cmd(ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
-
-	PERF_TRACE();
-}
 static void apply_symclk_on_tx_off_wa(struct dc_link *link)
 {
 	/* There are use cases where SYMCLK is referenced by OTG. For instance