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authorAlex Deucher <alexander.deucher@amd.com>2021-01-04 19:24:20 +0300
committerAlex Deucher <alexander.deucher@amd.com>2021-01-07 00:24:10 +0300
commitc241ed2f0ea549c18cff62a3708b43846b84dae3 (patch)
tree5f4f1c5788bd707ba9b1059eb93a84beb71a49bf /drivers/gpu/drm/amd/display/dc/calcs/Makefile
parent3851c90b7aa8f0c275d14636f0e7ccca69a2bf84 (diff)
downloadlinux-c241ed2f0ea549c18cff62a3708b43846b84dae3.tar.xz
drm/amdgpu/display: drop DCN support for aarch64
From Ard: "Simply disabling -mgeneral-regs-only left and right is risky, given that the standard AArch64 ABI permits the use of FP/SIMD registers anywhere, and GCC is known to use SIMD registers for spilling, and may invent other uses of the FP/SIMD register file that have nothing to do with the floating point code in question. Note that putting kernel_neon_begin() and kernel_neon_end() around the code that does use FP is not sufficient here, the problem is in all the other code that may be emitted with references to SIMD registers in it. So the only way to do this properly is to put all floating point code in a separate compilation unit, and only compile that unit with -mgeneral-regs-only." Disable support until the code can be properly refactored to support this properly on aarch64. Acked-by: Will Deacon <will@kernel.org> Reported-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/calcs/Makefile')
-rw-r--r--drivers/gpu/drm/amd/display/dc/calcs/Makefile4
1 files changed, 0 insertions, 4 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/Makefile b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
index 64f515d74410..f3c00f479e1c 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
@@ -33,10 +33,6 @@ ifdef CONFIG_PPC64
calcs_ccflags := -mhard-float -maltivec
endif
-ifdef CONFIG_ARM64
-calcs_rcflags := -mgeneral-regs-only
-endif
-
ifdef CONFIG_CC_IS_GCC
ifeq ($(call cc-ifversion, -lt, 0701, y), y)
IS_OLD_GCC = 1