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| author | Jack Xiao <Jack.Xiao@amd.com> | 2020-03-20 07:03:08 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2022-05-04 17:03:45 +0300 |
| commit | 11f39576ac807d39b1e7e7a3842eb55c387607bb (patch) | |
| tree | 81f6178030f177755e7d0eb11353b2c41e71c09d /drivers/gpu/drm/amd/amdgpu | |
| parent | 34ec3c2e0ef2fb6b60e42782caf19201de1372db (diff) | |
| download | linux-11f39576ac807d39b1e7e7a3842eb55c387607bb.tar.xz | |
drm/amdgpu/gfx10: associate mes queue id with fence v2
Associate mes queue id with fence, so that EOP trap handler can look up
which queue has issued the fence.
v2: move mes queue flag to amdgpu_mes_ctx.h
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_mes_ctx.h | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 3 |
2 files changed, 4 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes_ctx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes_ctx.h index f3e1ba1a889f..544f1aa86edf 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes_ctx.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes_ctx.h @@ -115,4 +115,6 @@ struct amdgpu_mes_ctx_data { #define AMDGPU_FENCE_MES_QUEUE_FLAG 0x1000000u #define AMDGPU_FENCE_MES_QUEUE_ID_MASK (AMDGPU_FENCE_MES_QUEUE_FLAG - 1) +#define AMDGPU_FENCE_MES_QUEUE_FLAG 0x1000000u + #endif diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index d06807355f5f..e6e601296097 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -8678,7 +8678,8 @@ static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, amdgpu_ring_write(ring, upper_32_bits(addr)); amdgpu_ring_write(ring, lower_32_bits(seq)); amdgpu_ring_write(ring, upper_32_bits(seq)); - amdgpu_ring_write(ring, 0); + amdgpu_ring_write(ring, ring->is_mes_queue ? + (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0); } static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) |