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authorKen Wang <Qingqing.Wang@amd.com>2015-06-03 16:02:01 +0300
committerAlex Deucher <alexander.deucher@amd.com>2015-06-04 04:04:04 +0300
commit81c59f54125f9ff84546b6ba26c321662562703d (patch)
tree5155dcf6e4f917f073d401342b412691e9757383 /drivers/gpu/drm/amd/amdgpu/vid.h
parent71062f435eaf0ff7867a1188e5c7887b0a5871ff (diff)
downloadlinux-81c59f54125f9ff84546b6ba26c321662562703d.tar.xz
drm/amdgpu: add vram_type and vram_bit_width for interface query (v2)
Track the type of vram on the board and provide a query for it. User mode drivers and tools want this information for determining bandwidth information and form informational purposes. v2: fix build when CI support is not enabled Signed-off-by: Ken Wang <Qingqing.Wang@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/vid.h')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vid.h11
1 files changed, 8 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/vid.h b/drivers/gpu/drm/amd/amdgpu/vid.h
index 385267c31d11..31bb89452e12 100644
--- a/drivers/gpu/drm/amd/amdgpu/vid.h
+++ b/drivers/gpu/drm/amd/amdgpu/vid.h
@@ -68,9 +68,14 @@
#define RB_BITMAP_WIDTH_PER_SH 2
-#define MC_SEQ_MISC0__GDDR5__SHIFT 0x1c
-#define MC_SEQ_MISC0__GDDR5_MASK 0xf0000000
-#define MC_SEQ_MISC0__GDDR5_VALUE 5
+#define MC_SEQ_MISC0__MT__MASK 0xf0000000
+#define MC_SEQ_MISC0__MT__GDDR1 0x10000000
+#define MC_SEQ_MISC0__MT__DDR2 0x20000000
+#define MC_SEQ_MISC0__MT__GDDR3 0x30000000
+#define MC_SEQ_MISC0__MT__GDDR4 0x40000000
+#define MC_SEQ_MISC0__MT__GDDR5 0x50000000
+#define MC_SEQ_MISC0__MT__HBM 0x60000000
+#define MC_SEQ_MISC0__MT__DDR3 0xB0000000
/*
* PM4