diff options
| author | Rex Zhu <rex.zhu@amd.com> | 2018-07-05 11:34:13 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2018-07-10 22:16:39 +0300 |
| commit | 73b1917454b3639ac1926c869f51e0dc20a0d22f (patch) | |
| tree | f17d07fe289e897ad5245eb6a80252841cb3803c /drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c | |
| parent | 02374bbd3bfa38cc6922fe56736716308c48f538 (diff) | |
| download | linux-73b1917454b3639ac1926c869f51e0dc20a0d22f.tar.xz | |
drm/amdgpu: Add CLK IP base offset
so we can read/write the registers in CLK domain
through RREG32/WREG32_SOC15
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c b/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c index 45aafca7f315..c5c9b2bc190d 100644 --- a/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c +++ b/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c @@ -51,6 +51,7 @@ int vega10_reg_base_init(struct amdgpu_device *adev) adev->reg_offset[PWR_HWIP][i] = (uint32_t *)(&(PWR_BASE.instance[i])); adev->reg_offset[NBIF_HWIP][i] = (uint32_t *)(&(NBIF_BASE.instance[i])); adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i])); + adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i])); } return 0; } |