drm/amdgpu: rename amdgpu_ip_funcs to amd_ip_funcs (v2)

The structure is renamed and moved to amd_shared.h to make
the component independent.  This makes it easier to add
new components in the future.

v2: fix include path

Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: yanyang1 <young.yang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 35 insertions, 18 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
index 6e4cb604f928..292932a73c81 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
@@ -83,17 +83,20 @@ static void uvd_v4_2_ring_set_wptr(struct amdgpu_ring *ring)
 	WREG32(mmUVD_RBC_RB_WPTR, ring->wptr);
 }
 
-static int uvd_v4_2_early_init(struct amdgpu_device *adev)
+static int uvd_v4_2_early_init(void *handle)
 {
+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
 	uvd_v4_2_set_ring_funcs(adev);
 	uvd_v4_2_set_irq_funcs(adev);
 
 	return 0;
 }
 
-static int uvd_v4_2_sw_init(struct amdgpu_device *adev)
+static int uvd_v4_2_sw_init(void *handle)
 {
 	struct amdgpu_ring *ring;
+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 	int r;
 
 	/* UVD TRAP */
@@ -117,9 +120,10 @@ static int uvd_v4_2_sw_init(struct amdgpu_device *adev)
 	return r;
 }
 
-static int uvd_v4_2_sw_fini(struct amdgpu_device *adev)
+static int uvd_v4_2_sw_fini(void *handle)
 {
 	int r;
+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
 	r = amdgpu_uvd_suspend(adev);
 	if (r)
@@ -139,8 +143,9 @@ static int uvd_v4_2_sw_fini(struct amdgpu_device *adev)
  *
  * Initialize the hardware, boot up the VCPU and do some testing
  */
-static int uvd_v4_2_hw_init(struct amdgpu_device *adev)
+static int uvd_v4_2_hw_init(void *handle)
 {
+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 	struct amdgpu_ring *ring = &adev->uvd.ring;
 	uint32_t tmp;
 	int r;
@@ -203,8 +208,9 @@ done:
  *
  * Stop the UVD block, mark ring as not ready any more
  */
-static int uvd_v4_2_hw_fini(struct amdgpu_device *adev)
+static int uvd_v4_2_hw_fini(void *handle)
 {
+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 	struct amdgpu_ring *ring = &adev->uvd.ring;
 
 	uvd_v4_2_stop(adev);
@@ -213,9 +219,10 @@ static int uvd_v4_2_hw_fini(struct amdgpu_device *adev)
 	return 0;
 }
 
-static int uvd_v4_2_suspend(struct amdgpu_device *adev)
+static int uvd_v4_2_suspend(void *handle)
 {
 	int r;
+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
 	r = uvd_v4_2_hw_fini(adev);
 	if (r)
@@ -228,9 +235,10 @@ static int uvd_v4_2_suspend(struct amdgpu_device *adev)
 	return r;
 }
 
-static int uvd_v4_2_resume(struct amdgpu_device *adev)
+static int uvd_v4_2_resume(void *handle)
 {
 	int r;
+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
 	r = amdgpu_uvd_resume(adev);
 	if (r)
@@ -662,14 +670,17 @@ static void uvd_v4_2_init_cg(struct amdgpu_device *adev)
 	}
 }
 
-static bool uvd_v4_2_is_idle(struct amdgpu_device *adev)
+static bool uvd_v4_2_is_idle(void *handle)
 {
+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
 	return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
 }
 
-static int uvd_v4_2_wait_for_idle(struct amdgpu_device *adev)
+static int uvd_v4_2_wait_for_idle(void *handle)
 {
 	unsigned i;
+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
 	for (i = 0; i < adev->usec_timeout; i++) {
 		if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK))
@@ -678,8 +689,10 @@ static int uvd_v4_2_wait_for_idle(struct amdgpu_device *adev)
 	return -ETIMEDOUT;
 }
 
-static int uvd_v4_2_soft_reset(struct amdgpu_device *adev)
+static int uvd_v4_2_soft_reset(void *handle)
 {
+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
 	uvd_v4_2_stop(adev);
 
 	WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK,
@@ -689,8 +702,9 @@ static int uvd_v4_2_soft_reset(struct amdgpu_device *adev)
 	return uvd_v4_2_start(adev);
 }
 
-static void uvd_v4_2_print_status(struct amdgpu_device *adev)
+static void uvd_v4_2_print_status(void *handle)
 {
+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 	dev_info(adev->dev, "UVD 4.2 registers\n");
 	dev_info(adev->dev, "  UVD_SEMA_ADDR_LOW=0x%08X\n",
 		 RREG32(mmUVD_SEMA_ADDR_LOW));
@@ -810,12 +824,13 @@ static int uvd_v4_2_process_interrupt(struct amdgpu_device *adev,
 	return 0;
 }
 
-static int uvd_v4_2_set_clockgating_state(struct amdgpu_device *adev,
-					  enum amdgpu_clockgating_state state)
+static int uvd_v4_2_set_clockgating_state(void *handle,
+					  enum amd_clockgating_state state)
 {
 	bool gate = false;
+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-	if (state == AMDGPU_CG_STATE_GATE)
+	if (state == AMD_CG_STATE_GATE)
 		gate = true;
 
 	uvd_v4_2_enable_mgcg(adev, gate);
@@ -823,8 +838,8 @@ static int uvd_v4_2_set_clockgating_state(struct amdgpu_device *adev,
 	return 0;
 }
 
-static int uvd_v4_2_set_powergating_state(struct amdgpu_device *adev,
-					  enum amdgpu_powergating_state state)
+static int uvd_v4_2_set_powergating_state(void *handle,
+					  enum amd_powergating_state state)
 {
 	/* This doesn't actually powergate the UVD block.
 	 * That's done in the dpm code via the SMC.  This
@@ -833,7 +848,9 @@ static int uvd_v4_2_set_powergating_state(struct amdgpu_device *adev,
 	 * revisit this when there is a cleaner line between
 	 * the smc and the hw blocks
 	 */
-	if (state == AMDGPU_PG_STATE_GATE) {
+	 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+	if (state == AMD_PG_STATE_GATE) {
 		uvd_v4_2_stop(adev);
 		return 0;
 	} else {
@@ -841,7 +858,7 @@ static int uvd_v4_2_set_powergating_state(struct amdgpu_device *adev,
 	}
 }
 
-const struct amdgpu_ip_funcs uvd_v4_2_ip_funcs = {
+const struct amd_ip_funcs uvd_v4_2_ip_funcs = {
 	.early_init = uvd_v4_2_early_init,
 	.late_init = NULL,
 	.sw_init = uvd_v4_2_sw_init,