Merge tag 'drm-fixes-2023-05-12' of git://anongit.freedesktop.org/drm/drm

Pull drm fixes from Dave Airlie:
 "About the usual for this stage, bunch of amdgpu, a few i915 and a
  scattering of fixes across the board"

  dsc:
   - macro fixes

  simplefb:
   - fix VESA format

  scheduler:
   - timeout handling fix

  fbdev:
   - avoid potential out-of-bounds access in generic fbdev emulation

  ast:
   - improve AST2500+ compat on ARM

  mipi-dsi:
   - small mipi-dsi fix

  amdgpu:
   - VCN3 fixes
   - APUs always support PCI atomics
   - legacy power management fixes
   - DCN 3.1.4 fix
   - DCFCLK fix
   - fix several RAS irq refcount mismatches
   - GPU Reset fix
   - GFX 11.0.4 fix

  i915:
   - taint kernel when force_probe is used
   - NULL deref and div-by-zero fixes for display
   - GuC error capture fix for Xe devices"

* tag 'drm-fixes-2023-05-12' of git://anongit.freedesktop.org/drm/drm: (24 commits)
  drm/amdgpu: change gfx 11.0.4 external_id range
  drm/amdgpu/jpeg: Remove harvest checking for JPEG3
  drm/amdgpu/gfx: disable gfx9 cp_ecc_error_irq only when enabling legacy gfx ras
  drm/amd/pm: avoid potential UBSAN issue on legacy asics
  drm/i915: taint kernel when force probing unsupported devices
  drm/i915/dp: prevent potential div-by-zero
  drm/i915: Fix NULL ptr deref by checking new_crtc_state
  drm/i915/guc: Don't capture Gen8 regs on Xe devices
  drm/amdgpu: disable sdma ecc irq only when sdma RAS is enabled in suspend
  drm/amdgpu: Fix vram recover doesn't work after whole GPU reset (v2)
  drm/amdgpu: drop gfx_v11_0_cp_ecc_error_irq_funcs
  drm/amd/display: Enforce 60us prefetch for 200Mhz DCFCLK modes
  drm/amd/display: Add symclk workaround during disable link output
  drm/amd/pm: parse pp_handle under appropriate conditions
  drm/amdgpu: set gfx9 onwards APU atomics support to be true
  drm/amdgpu/nv: update VCN 3 max HEVC encoding resolution
  drm/sched: Check scheduler work queue before calling timeout handling
  drm/mipi-dsi: Set the fwnode for mipi_dsi_device
  drm/nouveau/disp: More DP_RECEIVER_CAP_SIZE array fixes
  drm/dsc: fix DP_DSC_MAX_BPP_DELTA_* macro values
  ...

1 files changed, 16 insertions, 6 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 98c826f1f89b..0fb6013441f0 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -98,6 +98,16 @@ static const struct amdgpu_video_codecs nv_video_codecs_decode =
 };
 
 /* Sienna Cichlid */
+static const struct amdgpu_video_codec_info sc_video_codecs_encode_array[] = {
+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2160, 0)},
+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 7680, 4352, 0)},
+};
+
+static const struct amdgpu_video_codecs sc_video_codecs_encode = {
+	.codec_count = ARRAY_SIZE(sc_video_codecs_encode_array),
+	.codec_array = sc_video_codecs_encode_array,
+};
+
 static const struct amdgpu_video_codec_info sc_video_codecs_decode_array_vcn0[] =
 {
 	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
@@ -136,8 +146,8 @@ static const struct amdgpu_video_codecs sc_video_codecs_decode_vcn1 =
 /* SRIOV Sienna Cichlid, not const since data is controlled by host */
 static struct amdgpu_video_codec_info sriov_sc_video_codecs_encode_array[] =
 {
-	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
-	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2160, 0)},
+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 7680, 4352, 0)},
 };
 
 static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array_vcn0[] =
@@ -237,12 +247,12 @@ static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode,
 		} else {
 			if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) {
 				if (encode)
-					*codecs = &nv_video_codecs_encode;
+					*codecs = &sc_video_codecs_encode;
 				else
 					*codecs = &sc_video_codecs_decode_vcn1;
 			} else {
 				if (encode)
-					*codecs = &nv_video_codecs_encode;
+					*codecs = &sc_video_codecs_encode;
 				else
 					*codecs = &sc_video_codecs_decode_vcn0;
 			}
@@ -251,14 +261,14 @@ static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode,
 	case IP_VERSION(3, 0, 16):
 	case IP_VERSION(3, 0, 2):
 		if (encode)
-			*codecs = &nv_video_codecs_encode;
+			*codecs = &sc_video_codecs_encode;
 		else
 			*codecs = &sc_video_codecs_decode_vcn0;
 		return 0;
 	case IP_VERSION(3, 1, 1):
 	case IP_VERSION(3, 1, 2):
 		if (encode)
-			*codecs = &nv_video_codecs_encode;
+			*codecs = &sc_video_codecs_encode;
 		else
 			*codecs = &yc_video_codecs_decode;
 		return 0;