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authorFei Shao <fshao@chromium.org>2024-12-04 17:25:38 +0300
committerChun-Kuang Hu <chunkuang.hu@kernel.org>2025-01-02 16:40:27 +0300
commitba5811562988652d88de7503b3bd12da063ae729 (patch)
tree0b979ecda5a105683f13360903aaa7c3f820b6b1 /drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
parent4f0d4a8218914da9e3bd56ec2cfb7a644472213d (diff)
downloadlinux-ba5811562988652d88de7503b3bd12da063ae729.tar.xz
drm/mediatek: dp: Support flexible length of DP calibration data
The DP calibration data is stored in nvmem cells, and the data layout is described in the `mtk_dp_efuse_fmt` arrays for each platform. There is no guarantee that the data is always a 4-length u32 cell array. For example, MT8188 has a data length of 3, preventing it from passing the preliminary check and undergoing calibration. Update the logic to support flexible data lengths. Specifically, we validate the length returned from `nvmem_cell_read()` against the platform-specific efuse format. If out-of-bound access is detected, fall back to the default calibration values. This likely indicates an error in either the efuse data length described in DT or the efuse format within the driver. Signed-off-by: Fei Shao <fshao@chromium.org> Reviewed-by: CK Hu <ck.hu@mediatek.com> Link: https://patchwork.kernel.org/project/dri-devel/patch/20241204142626.158395-1-fshao@chromium.org/ Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_object.c')
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