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| author | Thomas Gleixner <tglx@linutronix.de> | 2021-09-11 01:38:47 +0300 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2021-09-11 01:38:47 +0300 |
| commit | c2f4954c2d3fc4f77b46c67585e17a58df4ba8e4 (patch) | |
| tree | 533a2077028e02a851e51ad509a0aa3a9107999f /drivers/fpga/zynq-fpga.c | |
| parent | 4b92d4add5f6dcf21275185c997d6ecb800054cd (diff) | |
| parent | 926de8c4326c14fcf35f1de142019043597a4fac (diff) | |
| download | linux-c2f4954c2d3fc4f77b46c67585e17a58df4ba8e4.tar.xz | |
Merge branch 'linus' into smp/urgent
Ensure that all usage sites of get/put_online_cpus() except for the
struggler in drivers/thermal are gone. So the last user and the deprecated
inlines can be removed.
Diffstat (limited to 'drivers/fpga/zynq-fpga.c')
| -rw-r--r-- | drivers/fpga/zynq-fpga.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c index 07fa8d9ec675..9b75bd4f93d8 100644 --- a/drivers/fpga/zynq-fpga.c +++ b/drivers/fpga/zynq-fpga.c @@ -192,7 +192,7 @@ static void zynq_step_dma(struct zynq_fpga_priv *priv) /* Once the first transfer is queued we can turn on the ISR, future * calls to zynq_step_dma will happen from the ISR context. The - * dma_lock spinlock guarentees this handover is done coherently, the + * dma_lock spinlock guarantees this handover is done coherently, the * ISR enable is put at the end to avoid another CPU spinning in the * ISR on this lock. */ @@ -267,7 +267,7 @@ static int zynq_fpga_ops_write_init(struct fpga_manager *mgr, ctrl = zynq_fpga_read(priv, CTRL_OFFSET); if (!(ctrl & CTRL_SEC_EN_MASK)) { dev_err(&mgr->dev, - "System not secure, can't use crypted bitstreams\n"); + "System not secure, can't use encrypted bitstreams\n"); err = -EINVAL; goto out_err; } @@ -344,7 +344,7 @@ static int zynq_fpga_ops_write_init(struct fpga_manager *mgr, /* set configuration register with following options: * - enable PCAP interface - * - set throughput for maximum speed (if bistream not crypted) + * - set throughput for maximum speed (if bistream not encrypted) * - set CPU in user mode */ ctrl = zynq_fpga_read(priv, CTRL_OFFSET); |