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authorCosmin Tanislav <demonsingur@gmail.com>2024-02-07 06:36:50 +0300
committerJonathan Cameron <Jonathan.Cameron@huawei.com>2024-02-25 17:30:45 +0300
commit1b926914bbe4e30cb32f268893ef7d82a85275b8 (patch)
treed7abf5c3fceb6990393f9d8d0af10484670acf0f /drivers/fpga/xilinx-selectmap.c
parenta1c9f508db2543aae59ea2378b07a026f6c917cf (diff)
downloadlinux-1b926914bbe4e30cb32f268893ef7d82a85275b8.tar.xz
iio: accel: adxl367: fix DEVID read after reset
regmap_read_poll_timeout() will not sleep before reading, causing the first read to return -ENXIO on I2C, since the chip does not respond to it while it is being reset. The datasheet specifies that a soft reset operation has a latency of 7.5ms. Add a 15ms sleep between reset and reading the DEVID register, and switch to a simple regmap_read() call. Fixes: cbab791c5e2a ("iio: accel: add ADXL367 driver") Signed-off-by: Cosmin Tanislav <demonsingur@gmail.com> Reviewed-by: Nuno Sa <nuno.sa@analog.com> Link: https://lore.kernel.org/r/20240207033657.206171-1-demonsingur@gmail.com Cc: <Stable@vger.kernel.org> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Diffstat (limited to 'drivers/fpga/xilinx-selectmap.c')
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