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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2024-01-17 21:50:46 +0300 | 
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2024-01-17 21:50:46 +0300 | 
| commit | 4331f070267ae8f76db1abbc7f4eeed4f06ae817 (patch) | |
| tree | a17dc8034c988daef4e2070ebf1ea5b30bad7770 /drivers/fpga/tests/fpga-bridge-test.c | |
| parent | 6cff79f4b90a42d73f039564f09fa5d59ec3d8ab (diff) | |
| parent | cb51bfee7f62a8e26b694f9d84c0041b3e3ccc71 (diff) | |
| download | linux-4331f070267ae8f76db1abbc7f4eeed4f06ae817.tar.xz | |
Merge tag 'riscv-for-linus-6.8-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull RISC-V updates from Palmer Dabbelt:
 - Support for many new extensions in hwprobe, along with a handful of
   cleanups
 - Various cleanups to our page table handling code, so we alwayse use
   {READ,WRITE}_ONCE
 - Support for the which-cpus flavor of hwprobe
 - Support for XIP kernels has been resurrected
* tag 'riscv-for-linus-6.8-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (52 commits)
  riscv: hwprobe: export Zicond extension
  riscv: hwprobe: export Zacas ISA extension
  riscv: add ISA extension parsing for Zacas
  dt-bindings: riscv: add Zacas ISA extension description
  riscv: hwprobe: export Ztso ISA extension
  riscv: add ISA extension parsing for Ztso
  use linux/export.h rather than asm-generic/export.h
  riscv: Remove SHADOW_OVERFLOW_STACK_SIZE macro
  riscv; fix __user annotation in save_v_state()
  riscv: fix __user annotation in traps_misaligned.c
  riscv: Select ARCH_WANTS_NO_INSTR
  riscv: Remove obsolete rv32_defconfig file
  riscv: Allow disabling of BUILTIN_DTB for XIP
  riscv: Fixed wrong register in XIP_FIXUP_FLASH_OFFSET macro
  riscv: Make XIP bootable again
  riscv: Fix set_direct_map_default_noflush() to reset _PAGE_EXEC
  riscv: Fix module_alloc() that did not reset the linear mapping permissions
  riscv: Fix wrong usage of lm_alias() when splitting a huge linear mapping
  riscv: Check if the code to patch lies in the exit section
  riscv: Use the same CPU operations for all CPUs
  ...
Diffstat (limited to 'drivers/fpga/tests/fpga-bridge-test.c')
0 files changed, 0 insertions, 0 deletions
