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| author | Abhishek Sahu <absahu@codeaurora.org> | 2017-12-13 17:25:36 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2017-12-22 03:03:31 +0300 |
| commit | b8e7e519625ffff27eb3a0c46974ef7b404d092d (patch) | |
| tree | ddb8c3a61b4c93d9a52d34068df3e3fb79a28359 /drivers/fpga/fpga-bridge.c | |
| parent | 8c1c2c5a9656ff17dc91da0a1dbe075fb912ba9b (diff) | |
| download | linux-b8e7e519625ffff27eb3a0c46974ef7b404d092d.tar.xz | |
clk: qcom: ipq8074: add remaining PLL’s
- GPLL2, GPLL4 and GPLL6 are general PLL clocks and parent
for all core peripherals.
- UBI PLL is mainly used by NSS (Network Switching System).
IPQ8074 has 2 instances of NSS UBI cores and UBI PLL will
be used to control the core frequency.
- NSS Crypto PLL is mainly used by NSS Crypto Engine which
supports the multiple cryptographic algorithm used in
Ethernet.
- IPQ8074 frequency plan does not require change in PLL post
dividers so marked the same as read-only.
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/fpga/fpga-bridge.c')
0 files changed, 0 insertions, 0 deletions