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| author | Yuantian Tang <andy.tang@nxp.com> | 2017-11-22 04:40:53 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2017-12-22 02:57:28 +0300 |
| commit | 36ab04671570fcd0e33868eba83f361d76c36bbf (patch) | |
| tree | 545b657ecd4c004d8f3e1d63e4b1d76b696a7c2b /drivers/fpga/fpga-bridge.c | |
| parent | 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323 (diff) | |
| download | linux-36ab04671570fcd0e33868eba83f361d76c36bbf.tar.xz | |
clk: qoriq: add more divider clocks support
More divider clocks are needed by IP. So enlarge the PLL divider
array to accommodate more divider clocks.
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/fpga/fpga-bridge.c')
0 files changed, 0 insertions, 0 deletions