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| author | Nicholas Piggin <npiggin@gmail.com> | 2019-03-07 00:28:31 +0300 |
|---|---|---|
| committer | Ley Foon Tan <ley.foon.tan@intel.com> | 2019-03-07 01:00:48 +0300 |
| commit | 21e6bff5e0ef0033d776e64c40e6873d7c75e74b (patch) | |
| tree | 501dd4adec10abc825735b5d44bcdebc8c721cd5 /drivers/fpga/altera-fpga2sdram.c | |
| parent | 3ac23944de570df7a6309425aeef063be38f37c4 (diff) | |
| download | linux-21e6bff5e0ef0033d776e64c40e6873d7c75e74b.tar.xz | |
nios2: Fix update_mmu_cache preload the TLB with the new PTE
There is a bug in the TLB preload caused by the pid not being
shifted to the correct location in tlbmisc register.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Diffstat (limited to 'drivers/fpga/altera-fpga2sdram.c')
0 files changed, 0 insertions, 0 deletions