diff options
| author | Russ Weight <russell.h.weight@intel.com> | 2022-06-06 19:00:35 +0300 |
|---|---|---|
| committer | Xu Yilun <yilun.xu@intel.com> | 2022-06-08 12:04:37 +0300 |
| commit | bdf86d0e6ca307de8c85e9363b31ca8c86c0b0c7 (patch) | |
| tree | 66d81cfa1292c584a941aa4f35c2ab7139721be7 /drivers/fpga/Makefile | |
| parent | 3f83b62a7bfa273959cb124bb581a20a68d114c3 (diff) | |
| download | linux-bdf86d0e6ca307de8c85e9363b31ca8c86c0b0c7.tar.xz | |
fpga: m10bmc-sec: create max10 bmc secure update
Create a sub-driver for the FPGA Card BMC in order to support secure
updates. This patch creates the Max10 BMC Secure Update driver and
provides sysfs files for displaying the root entry hashes (REH) for the
FPGA static region (SR), the FPGA Partial Reconfiguration (PR) region,
and the card BMC.
The Intel MAX10 BMC Root of Trust (RoT) requires that all BMC Nios firmware
and FPGA images are authenticated using ECDSA before loading and executing
on the card. Code Signing Keys (CSK) are used to sign images. CSKs are
signed by a root key. The root entry hash is created from the root public
key.
The RoT provides authentication by storing an REH bitstream to a write-once
location. Image signatures are verified against the hash.
Reviewed-by: Tom Rix <trix@redhat.com>
Tested-by: Tianfei Zhang <tianfei.zhang@intel.com>
Signed-off-by: Russ Weight <russell.h.weight@intel.com>
Link: https://lore.kernel.org/r/20220606160038.846236-3-russell.h.weight@intel.com
Signed-off-by: Xu Yilun <yilun.xu@intel.com>
Diffstat (limited to 'drivers/fpga/Makefile')
| -rw-r--r-- | drivers/fpga/Makefile | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index 5935b3d0abd5..139ac1b573d3 100644 --- a/drivers/fpga/Makefile +++ b/drivers/fpga/Makefile @@ -22,6 +22,9 @@ obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA) += versal-fpga.o obj-$(CONFIG_ALTERA_PR_IP_CORE) += altera-pr-ip-core.o obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT) += altera-pr-ip-core-plat.o +# FPGA Secure Update Drivers +obj-$(CONFIG_FPGA_M10_BMC_SEC_UPDATE) += intel-m10-bmc-sec-update.o + # FPGA Bridge Drivers obj-$(CONFIG_FPGA_BRIDGE) += fpga-bridge.o obj-$(CONFIG_SOCFPGA_FPGA_BRIDGE) += altera-hps2fpga.o altera-fpga2sdram.o |