Merge tag 'pinctrl-v5.13-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij:
 "There is a lot going on!

  Core changes:

   - A semantic change to handle pinmux and pinconf in explicit order
     while up until now we depended on the semantic order in the device
     tree. The device tree is a functional programming language and does
     not imply any order, so the right thing is for the pin control core
     to provide these semantics.

   - Add a new pinmux-select debugfs file which makes it possible to go
     in and select functions for a pin manually (iteratively, at the
     prompt) for debugging purposes.

   - Fixes to gpio regmap handling for a new pin control driver making
     use of regmap-gpio.

   - Use octal permissions on debugfs files.

  New drivers:

   - A massive rewrite of the former custom pin control driver for MIPS
     Broadcom devices to instead use the pin control subsystem. New pin
     control drivers for BCM6345, BCM6328, BCM6358, BCM6362, BCM6368,
     BCM63268 and BCM6318 SoC variants are implemented.

   - Support for PM8350, PM8350B, PM8350C, PMK8350, PMR735A and PMR735B
     in the Qualcomm PMIC GPIO driver. Also the two GPIOs on PM8008 are
     supported.

   - Support for the Rockchip RK3568/RK3566 pin controller.

   - Support for Ingenic JZ4730, JZ4750, JZ4755, JZ4775 and X2000.

   - Support for Mediatek MTK8195.

   - Add a new Xilinx ZynqMP pin control driver.

  Driver improvements and non-urgent fixes:

   - Modularization and improvements of the Rockchip drivers.

   - Some new pins added to the description of new Renesas SoCs.

   - Clarifications of the GPIO base calculation in the Intel driver.

   - Fix the function names for the MPP54 and MPP55 pins in the Armada
     CP110 pin controller.

   - GPIO wakeup interrupt map for Qualcomm SC7280 and SM8350.

   - Support for ACPI probing of the Qualcomm SC8180x.

   - Fix interrupt clear status on rockchip

   - Fix some missing pins on the Ingenic JZ4770, some semantic fixes
     for the behaviour of the Ingenic pin controller. Add DMIC pins for
     JZ4780, X1000, X1500 and X1830.

   - A slew of janitorial like of_node_put() calls"

* tag 'pinctrl-v5.13-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (99 commits)
  pinctrl: Add Xilinx ZynqMP pinctrl driver support
  firmware: xilinx: Add pinctrl support
  pinctrl: rockchip: do coding style for mux route struct
  pinctrl: Add PIN_CONFIG_MODE_PWM to enum pin_config_param
  pinctrl: Introduce MODE group in enum pin_config_param
  pinctrl: Keep enum pin_config_param ordered by name
  dt-bindings: pinctrl: Add binding for ZynqMP pinctrl driver
  pinctrl: core: Fix kernel doc string for pin_get_name()
  pinctrl: mediatek: use spin lock in mtk_rmw
  pinctrl: add drive for I2C related pins on MT8195
  pinctrl: add pinctrl driver on mt8195
  dt-bindings: pinctrl: mt8195: add pinctrl file and binding document
  pinctrl: Ingenic: Add pinctrl driver for X2000.
  pinctrl: Ingenic: Add pinctrl driver for JZ4775.
  pinctrl: Ingenic: Add pinctrl driver for JZ4755.
  pinctrl: Ingenic: Add pinctrl driver for JZ4750.
  pinctrl: Ingenic: Add pinctrl driver for JZ4730.
  dt-bindings: pinctrl: Add bindings for new Ingenic SoCs.
  pinctrl: Ingenic: Reformat the code.
  pinctrl: Ingenic: Add DMIC pins support for Ingenic SoCs.
  ...

1 files changed, 114 insertions, 0 deletions

diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
index 83082e2f2e44..15b138326ecc 100644
--- a/drivers/firmware/xilinx/zynqmp.c
+++ b/drivers/firmware/xilinx/zynqmp.c
@@ -812,6 +812,120 @@ int zynqmp_pm_fpga_get_status(u32 *value)
 EXPORT_SYMBOL_GPL(zynqmp_pm_fpga_get_status);
 
 /**
+ * zynqmp_pm_pinctrl_request - Request Pin from firmware
+ * @pin: Pin number to request
+ *
+ * This function requests pin from firmware.
+ *
+ * Return: Returns status, either success or error+reason.
+ */
+int zynqmp_pm_pinctrl_request(const u32 pin)
+{
+	return zynqmp_pm_invoke_fn(PM_PINCTRL_REQUEST, pin, 0, 0, 0, NULL);
+}
+EXPORT_SYMBOL_GPL(zynqmp_pm_pinctrl_request);
+
+/**
+ * zynqmp_pm_pinctrl_release - Inform firmware that Pin control is released
+ * @pin: Pin number to release
+ *
+ * This function release pin from firmware.
+ *
+ * Return: Returns status, either success or error+reason.
+ */
+int zynqmp_pm_pinctrl_release(const u32 pin)
+{
+	return zynqmp_pm_invoke_fn(PM_PINCTRL_RELEASE, pin, 0, 0, 0, NULL);
+}
+EXPORT_SYMBOL_GPL(zynqmp_pm_pinctrl_release);
+
+/**
+ * zynqmp_pm_pinctrl_get_function - Read function id set for the given pin
+ * @pin: Pin number
+ * @id: Buffer to store function ID
+ *
+ * This function provides the function currently set for the given pin.
+ *
+ * Return: Returns status, either success or error+reason
+ */
+int zynqmp_pm_pinctrl_get_function(const u32 pin, u32 *id)
+{
+	u32 ret_payload[PAYLOAD_ARG_CNT];
+	int ret;
+
+	if (!id)
+		return -EINVAL;
+
+	ret = zynqmp_pm_invoke_fn(PM_PINCTRL_GET_FUNCTION, pin, 0,
+				  0, 0, ret_payload);
+	*id = ret_payload[1];
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(zynqmp_pm_pinctrl_get_function);
+
+/**
+ * zynqmp_pm_pinctrl_set_function - Set requested function for the pin
+ * @pin: Pin number
+ * @id: Function ID to set
+ *
+ * This function sets requested function for the given pin.
+ *
+ * Return: Returns status, either success or error+reason.
+ */
+int zynqmp_pm_pinctrl_set_function(const u32 pin, const u32 id)
+{
+	return zynqmp_pm_invoke_fn(PM_PINCTRL_SET_FUNCTION, pin, id,
+				   0, 0, NULL);
+}
+EXPORT_SYMBOL_GPL(zynqmp_pm_pinctrl_set_function);
+
+/**
+ * zynqmp_pm_pinctrl_get_config - Get configuration parameter for the pin
+ * @pin: Pin number
+ * @param: Parameter to get
+ * @value: Buffer to store parameter value
+ *
+ * This function gets requested configuration parameter for the given pin.
+ *
+ * Return: Returns status, either success or error+reason.
+ */
+int zynqmp_pm_pinctrl_get_config(const u32 pin, const u32 param,
+				 u32 *value)
+{
+	u32 ret_payload[PAYLOAD_ARG_CNT];
+	int ret;
+
+	if (!value)
+		return -EINVAL;
+
+	ret = zynqmp_pm_invoke_fn(PM_PINCTRL_CONFIG_PARAM_GET, pin, param,
+				  0, 0, ret_payload);
+	*value = ret_payload[1];
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(zynqmp_pm_pinctrl_get_config);
+
+/**
+ * zynqmp_pm_pinctrl_set_config - Set configuration parameter for the pin
+ * @pin: Pin number
+ * @param: Parameter to set
+ * @value: Parameter value to set
+ *
+ * This function sets requested configuration parameter for the given pin.
+ *
+ * Return: Returns status, either success or error+reason.
+ */
+int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param,
+				 u32 value)
+{
+	return zynqmp_pm_invoke_fn(PM_PINCTRL_CONFIG_PARAM_SET, pin,
+				   param, value, 0, NULL);
+}
+EXPORT_SYMBOL_GPL(zynqmp_pm_pinctrl_set_config);
+
+/**
  * zynqmp_pm_init_finalize() - PM call to inform firmware that the caller
  *			       master has initialized its own power management
  *