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authorAndy Hu <andy.hu@starfivetech.com>2022-12-19 10:12:22 +0300
committerAndy Hu <andy.hu@starfivetech.com>2022-12-19 10:12:22 +0300
commitf0fce0037f9cc3fa6013d14d2f11fff7cf1a19da (patch)
treeb1c279c003c2ce2bd80212637ed76ca49b614070 /drivers/clk
parent40befeb85a659c53cc08fcfc7458a47dbc01597a (diff)
parentb85f8dd876e2e579b169c397a03ff41b6dff9489 (diff)
downloadlinux-VF2_v2.5.0.tar.xz
Merge tag 'JH7110_515_SDK_v3.5.1' from sdk into vf2-515-develVF2_v2.5.0
version JH7110_515_SDK_v3.5.1 for JH7110 EVB board
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/starfive/clk-starfive-jh7110-gen.c2
-rw-r--r--drivers/clk/starfive/clk-starfive-jh7110-pll.h26
2 files changed, 4 insertions, 24 deletions
diff --git a/drivers/clk/starfive/clk-starfive-jh7110-gen.c b/drivers/clk/starfive/clk-starfive-jh7110-gen.c
index cf974d2ffa38..d852c0a2d01f 100644
--- a/drivers/clk/starfive/clk-starfive-jh7110-gen.c
+++ b/drivers/clk/starfive/clk-starfive-jh7110-gen.c
@@ -392,7 +392,7 @@ static int __init clk_starfive_jh7110_probe(struct platform_device *pdev)
if (PLL0_DEFAULT_FREQ >= PLL0_FREQ_1500_VALUE) {
struct clk *cpu_core = priv->reg[JH7110_CPU_CORE].hw.clk;
- if (clk_set_rate(cpu_core, PLL0_FREQ_1500_VALUE / 2)) {
+ if (clk_set_rate(cpu_core, clk_get_rate(pll0_clk) / 2)) {
dev_err(&pdev->dev, "set cpu_core rate failed\n");
goto failed_set;
}
diff --git a/drivers/clk/starfive/clk-starfive-jh7110-pll.h b/drivers/clk/starfive/clk-starfive-jh7110-pll.h
index 1668c222752f..87843181ecf8 100644
--- a/drivers/clk/starfive/clk-starfive-jh7110-pll.h
+++ b/drivers/clk/starfive/clk-starfive-jh7110-pll.h
@@ -125,9 +125,7 @@ enum starfive_pll0_freq_value {
PLL0_FREQ_1000_VALUE = 1000000000,
PLL0_FREQ_1250_VALUE = 1250000000,
PLL0_FREQ_1375_VALUE = 1375000000,
- PLL0_FREQ_1500_VALUE = 1500000000,
- PLL0_FREQ_1625_VALUE = 1625000000,
- PLL0_FREQ_1750_VALUE = 1750000000
+ PLL0_FREQ_1500_VALUE = 1500000000
};
enum starfive_pll0_freq {
@@ -140,9 +138,7 @@ enum starfive_pll0_freq {
PLL0_FREQ_1250,
PLL0_FREQ_1375,
PLL0_FREQ_1500,
- PLL0_FREQ_1625,
- PLL0_FREQ_1750,
- PLL0_FREQ_MAX
+ PLL0_FREQ_MAX = PLL0_FREQ_1500
};
enum starfive_pll1_freq_value {
@@ -164,7 +160,7 @@ enum starfive_pll2_freq {
};
static const struct starfive_pll_syscon_value
- jh7110_pll0_syscon_freq[PLL0_FREQ_MAX] = {
+ jh7110_pll0_syscon_freq[] = {
[PLL0_FREQ_375] = {
.freq = PLL0_FREQ_375_VALUE,
.prediv = 8,
@@ -237,22 +233,6 @@ static const struct starfive_pll_syscon_value
.dacpd = 1,
.dsmpd = 1,
},
- [PLL0_FREQ_1625] = {
- .freq = PLL0_FREQ_1625_VALUE,
- .prediv = 24,
- .fbdiv = 1625,
- .postdiv1 = 1,
- .dacpd = 1,
- .dsmpd = 1,
- },
- [PLL0_FREQ_1750] = {
- .freq = PLL0_FREQ_1750_VALUE,
- .prediv = 12,
- .fbdiv = 875,
- .postdiv1 = 1,
- .dacpd = 1,
- .dsmpd = 1,
- },
};
static const struct starfive_pll_syscon_value