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| author | Luo Jie <quic_luoj@quicinc.com> | 2024-06-05 15:45:39 +0300 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2024-06-13 07:04:26 +0300 |
| commit | 80bbd1c355d661678d2a25bd36e739b6925e7a4e (patch) | |
| tree | fcc41db56aad1878c6492a6d5456650f44167074 /drivers/clk/qcom/tcsrcc-sm8550.c | |
| parent | 7311bbfff31c4961c57d94c165fa843f155f8236 (diff) | |
| download | linux-80bbd1c355d661678d2a25bd36e739b6925e7a4e.tar.xz | |
dt-bindings: clock: add qca8386/qca8084 clock and reset definitions
QCA8386/QCA8084 includes the clock & reset controller that is
accessed by MDIO bus. Two work modes are supported, qca8386 works
as switch mode, qca8084 works as PHY mode.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
Link: https://lore.kernel.org/r/20240605124541.2711467-3-quic_luoj@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'drivers/clk/qcom/tcsrcc-sm8550.c')
0 files changed, 0 insertions, 0 deletions