diff options
| author | Stephen Boyd <sboyd@codeaurora.org> | 2014-07-11 23:55:27 +0400 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2014-07-16 03:38:59 +0400 |
| commit | 404c1ff67d241e8503fd46a09d324343aa321a8a (patch) | |
| tree | ef9e18a1029de024540d02550d1a99d162d164a1 /drivers/clk/qcom/clk-rcg.h | |
| parent | 24d8fba44af32163334c1f162e65ba93eb2993fd (diff) | |
| download | linux-404c1ff67d241e8503fd46a09d324343aa321a8a.tar.xz | |
clk: qcom: Support bypass RCG configuration
In the case of HDMI clocks, we want to bypass the RCG's ability
to divide the output clock and pass through the parent HDMI PLL
rate. Add a simple set of clk_ops to configure the RCG to do
this. This removes the need to keep adding more frequency entries
to the tv_src clock whenever we want to support a new rate.
Tested-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/qcom/clk-rcg.h')
| -rw-r--r-- | drivers/clk/qcom/clk-rcg.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h index b9ec11dfd1b4..ba0523cefd2e 100644 --- a/drivers/clk/qcom/clk-rcg.h +++ b/drivers/clk/qcom/clk-rcg.h @@ -95,6 +95,7 @@ struct clk_rcg { }; extern const struct clk_ops clk_rcg_ops; +extern const struct clk_ops clk_rcg_bypass_ops; #define to_clk_rcg(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg, clkr) |