diff options
| author | Doug Brown <doug@schmorgal.com> | 2022-06-12 22:29:33 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2022-09-30 23:34:06 +0300 |
| commit | d4161f7e7358eb3f20e6b82fa2ace19712ea5e6e (patch) | |
| tree | 8f8b23b935588fb97f1435c518b51de808597bd2 /drivers/clk/mmp | |
| parent | 7fad6b755fcb5fd4fe9127662cf41eb84d02fdb8 (diff) | |
| download | linux-d4161f7e7358eb3f20e6b82fa2ace19712ea5e6e.tar.xz | |
clk: mmp: pxa168: fix GPIO clock enable bits
According to the datasheet, only bit 0 of APBC_GPIO should be controlled
for the clock enable. Bit 1 is marked as reserved (always write 0).
Signed-off-by: Doug Brown <doug@schmorgal.com>
Link: https://lore.kernel.org/r/20220612192937.162952-9-doug@schmorgal.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/mmp')
| -rw-r--r-- | drivers/clk/mmp/clk-of-pxa168.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/mmp/clk-of-pxa168.c b/drivers/clk/mmp/clk-of-pxa168.c index 5e31cec345d9..d63ca6c9dffa 100644 --- a/drivers/clk/mmp/clk-of-pxa168.c +++ b/drivers/clk/mmp/clk-of-pxa168.c @@ -179,7 +179,7 @@ static struct mmp_param_mux_clk apbc_mux_clks[] = { static struct mmp_param_gate_clk apbc_gate_clks[] = { {PXA168_CLK_TWSI0, "twsi0_clk", "twsi0_mux", CLK_SET_RATE_PARENT, APBC_TWSI0, 0x3, 0x3, 0x0, 0, &twsi0_lock}, {PXA168_CLK_TWSI1, "twsi1_clk", "twsi1_mux", CLK_SET_RATE_PARENT, APBC_TWSI1, 0x3, 0x3, 0x0, 0, &twsi1_lock}, - {PXA168_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_GPIO, 0x3, 0x3, 0x0, 0, &reset_lock}, + {PXA168_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_GPIO, 0x1, 0x1, 0x0, 0, &reset_lock}, {PXA168_CLK_KPC, "kpc_clk", "kpc_mux", CLK_SET_RATE_PARENT, APBC_KPC, 0x3, 0x3, 0x0, MMP_CLK_GATE_NEED_DELAY, &kpc_lock}, {PXA168_CLK_RTC, "rtc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_RTC, 0x83, 0x83, 0x0, MMP_CLK_GATE_NEED_DELAY, NULL}, {PXA168_CLK_PWM0, "pwm0_clk", "pwm0_mux", CLK_SET_RATE_PARENT, APBC_PWM0, 0x3, 0x3, 0x0, 0, &pwm0_lock}, |