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| author | Matthew Auld <matthew.auld@intel.com> | 2023-01-26 14:31:34 +0300 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2023-12-20 02:27:44 +0300 |
| commit | 5e53d1e806aeb2b05c85d24cd75f848631e8a121 (patch) | |
| tree | e3f181d3f16f09aa3aa8c2eccbedd71d36a834df /drivers/bus | |
| parent | b1e52b65712969a74f0ba9ffbf67dde98ce33c2f (diff) | |
| download | linux-5e53d1e806aeb2b05c85d24cd75f848631e8a121.tar.xz | |
drm/xe/ggtt: fix alignment usage for DG2
Spec says we need to use 64K VRAM pages for GGTT on platforms like DG2.
In GGTT this just means aligning the GTT address to 64K and ensuring
that we have 16 consecutive entries each pointing to the respective 4K
entry. We already ensure we have 64K pages underneath, so it's just a
case of forcing the GTT alignment.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/bus')
0 files changed, 0 insertions, 0 deletions