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| author | Dongdong Liu <liudongdong3@huawei.com> | 2016-12-01 09:45:35 +0300 |
|---|---|---|
| committer | Bjorn Helgaas <helgaas@kernel.org> | 2016-12-06 22:45:49 +0300 |
| commit | 5f00f1a0178cf52928366a5e1f376a65f1f3f389 (patch) | |
| tree | 94a3a7b9cdfae44cd1410920f3111f893a2295cb /drivers/acpi/pci_mcfg.c | |
| parent | 2ca5b8ddc6f70d77a51851ba5e5cd0d39c27dd88 (diff) | |
| download | linux-5f00f1a0178cf52928366a5e1f376a65f1f3f389.tar.xz | |
PCI: Add MCFG quirks for HiSilicon Hip05/06/07 host controllers
The PCIe controller in Hip05/Hip06/Hip07 SoCs is not completely
ECAM-compliant. It is non-ECAM only for the RC bus config space; for any
other bus underneath the root bus it does support ECAM access.
Add specific quirks for PCI config space accessors. This involves:
1. New initialization call hisi_pcie_init() to obtain RC base
addresses from PNP0C02 at the root of the ACPI namespace (under \_SB).
2. New entry in common quirk array.
[bhelgaas: move to pcie-hisi.c and change Makefile/ifdefs so quirk doesn't
depend on CONFIG_PCI_HISI]
Signed-off-by: Dongdong Liu <liudongdong3@huawei.com>
Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'drivers/acpi/pci_mcfg.c')
| -rw-r--r-- | drivers/acpi/pci_mcfg.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c index cee33b078d3d..dd162248c3ee 100644 --- a/drivers/acpi/pci_mcfg.c +++ b/drivers/acpi/pci_mcfg.c @@ -62,6 +62,18 @@ static struct mcfg_fixup mcfg_quirks[] = { QCOM_ECAM32(5), QCOM_ECAM32(6), QCOM_ECAM32(7), + +#define HISI_QUAD_DOM(table_id, seg, ops) \ + { "HISI ", table_id, 0, (seg) + 0, MCFG_BUS_ANY, ops }, \ + { "HISI ", table_id, 0, (seg) + 1, MCFG_BUS_ANY, ops }, \ + { "HISI ", table_id, 0, (seg) + 2, MCFG_BUS_ANY, ops }, \ + { "HISI ", table_id, 0, (seg) + 3, MCFG_BUS_ANY, ops } + HISI_QUAD_DOM("HIP05 ", 0, &hisi_pcie_ops), + HISI_QUAD_DOM("HIP06 ", 0, &hisi_pcie_ops), + HISI_QUAD_DOM("HIP07 ", 0, &hisi_pcie_ops), + HISI_QUAD_DOM("HIP07 ", 4, &hisi_pcie_ops), + HISI_QUAD_DOM("HIP07 ", 8, &hisi_pcie_ops), + HISI_QUAD_DOM("HIP07 ", 12, &hisi_pcie_ops), }; static char mcfg_oem_id[ACPI_OEM_ID_SIZE]; |